24AA044 Datasheet, PDF (8/32 Pages) Microchip Technology – 4K I2C™ Serial EEPROM

24AA044
6.0 WRITE OPERATIONS
6.1 Byte Write
Following the Start signal from the master, the device
code (4 bits), the Chip Select bits (2 bits), the block
select bit (1 bit), and the R/W bit (which is a logic-low)
is placed onto the bus by the master transmitter. The
device will acknowledge this control byte during the
ninth clock pulse. The next byte transmitted by the
master is the array address and will be written into the
Address Pointer of the 24AA044. After receiving
another Acknowledge signal from the 24AA044, the
master device will transmit the data byte to be written
into the addressed memory location. The 24AA044
acknowledges again and the master generates a Stop
condition. This initiates the internal write cycle and,
during this time, the 24AA044 will not generate
Acknowledge signals (Figure 6-1). If an attempt is
made to write to the protected portion of the array when
the hardware write protection has been enabled, the
device will acknowledge the command, but no data will
be written.
6.2 Page Write
The write control byte, array address and the first data
byte are transmitted to the 24AA044 in the same way
as in a byte write. However, instead of generating a
Stop condition, the master transmits up to 15 additional
data bytes to the 24AA044, which are temporarily
stored in the on-chip page buffer and will be written into
the memory once the master has transmitted a Stop
condition. Upon receipt of each byte, the four lower-
order Address Pointer bits are internally incremented
by one.
The higher-order five bits of the array address remain
constant. If the master should transmit more than 16
bytes prior to generating the Stop condition, the
address counter will roll over and the previously
FIGURE 6-1:
BYTE WRITE
S
BUS ACTIVITY
T
A
MASTER
R
T
Control
Byte
SDA LINE
S
received data will be overwritten. As with the byte-write
operation, once the Stop condition is received, an
internal write cycle will begin (Figure 6-2). If an attempt
is made to write to the protected portion of the array
when the hardware write protection has been enabled,
the device will acknowledge the command, but no data
will be written.
Note:
When doing a write of less than 16 bytes,
the data in the rest of the page is
refreshed along with the data bytes being
written. This will force the entire page to
endure a write cycle. For this reason,
endurance is specified per page.
Note:
Page write operations are limited to writ-
ing bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and end at addresses that
are integer multiples of [page size – 1]. If
a Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
6.3 Write Protection
The WP pin must be tied to VCC or VSS. If tied to VCC,
the entire array will be write-protected. If the WP pin is
tied to VSS, write operations to all address locations are
allowed.
Array
Address
S
Data
T
O
P
P
BUS ACTIVITY
FIGURE 6-2:
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
A
C
K
PAGE WRITE
S
T
A
Control
R
Byte
T
Array
Address (n)
S
A
A
C
C
K
K
Data (n)
A
C
K
Data (n +1)
A
A
C
C
K
K
A
C
K
S
T
Data (n + 15)
O
P
P
A
C
K
DS20005286A-page 8
 2014 Microchip Technology Inc.