24AA044 Datasheet, PDF (3/32 Pages) Microchip Technology – 4K I2C™ Serial EEPROM

24AA044
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V
Automotive (E): TA = -40°C to +125°C, VCC = +1.7V to +5.5V
Param.
No.
Symbol
Characteristic
Min.
Max. Units
Conditions
1
FCLK
Clock frequency
—
100
kHz 1.7V  VCC < 1.8V
—
400
1.8V  VCC < 2.2V
—
1000
2.2V  VCC < 5.5V
2
THIGH
Clock high time
4000
600
500
—
ns 1.7V  VCC < 1.8V
—
1.8V  VCC < 2.2V
—
2.2V  VCC < 5.5V
3
TLOW
Clock low time
4700
1300
500
—
ns 1.7V  VCC < 1.8V
—
1.8V  VCC < 2.2V
—
2.2V  VCC < 5.5V
4
TR
SDA and SCL rise time (Note 1)
—
1000
ns 1.7V  VCC < 1.8V
—
300
1.8V  VCC < 2.2V
—
300
2.2V  VCC < 5.5V
5
TF
SDA and SCL fall time (Note 1)
—
300
ns 1.7V  VCC < 1.8V
—
300
1.8V  VCC < 2.2V
—
100
2.2V  VCC < 5.5V
6
THD:STA Start condition hold time
4000
600
250
—
ns 1.7V  VCC < 1.8V
—
1.8V  VCC < 2.2V
—
2.2V  VCC < 5.5V
7
TSU:STA Start condition setup time
4700
600
250
—
ns 1.7V  VCC < 1.8V
—
1.8V  VCC < 2.2V
—
2.2V  VCC < 5.5V
8
THD:DAT Data input hold time
0
—
ns (Note 2)
9
TSU:DAT Data input setup time
250
—
ns 1.7V  VCC < 1.8V
100
—
1.8V  VCC < 2.2V
100
—
2.2V  VCC < 5.5V
10
TSU:STO Stop condition setup time
4000
600
250
—
ns 1.7V  VCC < 1.8V
—
1.8V  VCC < 2.2V
—
2.2V  VCC < 5.5V
11
TSU:WP WP setup time
4000
600
600
—
ns 1.7V  VCC < 1.8V
—
1.8V  VCC < 2.2V
—
2.2V  VCC < 5.5V
12
THD:WP WP hold time
4700
1300
1300
—
ns 1.7V  VCC < 1.8V
—
1.8V  VCC < 2.2V
—
2.2V  VCC < 5.5V
13
TAA
Output valid from clock (Note 2)
—
3500
ns 1.7V  VCC < 1.8V
—
900
1.8V  VCC < 2.2V
—
400
2.2V  VCC < 5.5V
14
TBUF
Bus free time: Time the bus must
4700
be free before a new transmission
1300
can start
500
—
ns 1.7V  VCC < 1.8V
—
1.8V  VCC < 2.2V
2.2V  VCC < 5.5V
15
TSP
Input filter spike suppression
(SDA and SCL pins)
—
50
ns (Note 1)
16
TWC
Write cycle time (byte or page)
—
5
ms —
17
—
Endurance
1M
—
cycles Page mode, 25°C, VCC = 5.5V
(Note 3)
Note 1: Not 100% tested.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
200 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please
consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
 2014 Microchip Technology Inc.
DS20005286A-page 3