24AA044 Datasheet, PDF (7/32 Pages) Microchip Technology – 4K I2C™ Serial EEPROM

5.0 DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consists of a 4-bit control code. For the
24AA044, this is set as ‘1010’ binary for read and write
operations. The next two bits of the control byte are the
Chip Select bits (A2, A1). The Chip Select bits allow the
use of up to four 24AA044 devices on the same bus
and are used to select which device is accessed. The
Chip Select bits in the control byte must correspond to
the logic levels on the corresponding A2 and A1 pins
for the device to respond. These bits are in effect the
two Most Significant bits of the array address.
The next bit of the control byte is the block select bit
(B0). This bit acts as the A8 address bit for accessing
the entire array.
The last bit of the control byte defines the operation to
be performed. When set to a one, a read operation is
selected. When set to a zero, a write operation is
selected. Following the Start condition, the 24AA044
monitors the SDA bus checking the control byte being
transmitted. Upon receiving a ‘1010’ code and appro-
priate Chip Select bits, the slave device outputs an
Acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24AA044 will select a read or
write operation.
24AA044
FIGURE 5-1:
CONTROL BYTE FORMAT
Control Code
Read/Write Bit
Chip Block
Select Select
Bits Bit
S 1 0 1 0 A2 A1 B0 R/W ACK
Start Bit
Slave Address
Acknowledge Bit
5.1 Contiguous Addressing Across
Multiple Devices
The Chip Select bits A2 and A1 can be used to expand
the contiguous address space for up to 16K bits by add-
ing up to four 24AA044 devices on the same bus. In this
case, software can use A1 of the control byte as
address bit A9, and A2 as address bit A10. It is not
possible to sequentially read across device
boundaries.
 2014 Microchip Technology Inc.
DS20005286A-page 7