24AA044 Datasheet, PDF (5/32 Pages) Microchip Technology – 4K I2C™ Serial EEPROM

24AA044
2.0 PIN DESCRIPTIONS
Pin Function Table
Name
PDIP
NC
1
A1
2
A2
3
VSS
4
SDA
5
SCL
6
WP
7
VCC
8
SOIC
1
2
3
4
5
6
7
8
TSSOP
1
2
3
4
5
6
7
8
UDFN
1
2
3
4
5
6
7
8
MSOP
1
2
3
4
5
6
7
8
Description
Not Connected
Chip Address Input
Chip Address Input
Ground
Serial Address/Data I/O
Serial Clock
Write-Protect Input
+1.7 to 5.5V Power Supply
2.1 Serial Data (SDA)
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open-drain
terminal; therefore, the SDA bus requires a pull-up
resistor to VCC (typical 10 k for 100 kHz, 2 k for
400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.2 Serial Clock (SCL)
The SCL input is used to synchronize the data transfer
from and to the device.
2.3 Chip Address Inputs (A1, A2)
The levels on the A1 and A2 inputs are compared with
the corresponding bits in the slave address. The chip is
selected if the compare is true.
Up to four 24AA044 devices may be connected to the
same bus by using different Chip Select bit combina-
tions. These inputs must be connected to either VCC or
VSS.
2.5 Noise Protection
The 24AA044 employs a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 1.35V at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
3.0 FUNCTIONAL DESCRIPTION
The 24AA044 supports a bidirectional, 2-wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, while a
device receiving data is defined as receiver. The bus
has to be controlled by a master device that gener-
ates the Serial Clock (SCL), controls the bus access
and generates the Start and Stop conditions, while
the 24AA044 works as slave. Both master and slave
can operate as transmitter or receiver, but the master
device determines which mode is activated.
2.4 Write-Protect (WP)
WP is the hardware write-protect pin. It must be tied to
VCC or VSS. If tied to Vcc, hardware write protection is
enabled. If WP is tied to Vss, the hardware write
protection is disabled.
 2014 Microchip Technology Inc.
DS20005286A-page 5