DSPIC30F2012-30I Datasheet, PDF (74/210 Pages) Microchip Technology – High-Performance, 16-bit Digital Signal Controllers

dsPIC30F2011/2012/3012/3013
9.1 Timer Gate Operation
The 16-bit timer can be placed in the Gated Time
Accumulation mode. This mode allows the internal TCY
to increment the respective timer when the gate input
signal (T1CK pin) is asserted high. Control bit,
TGATE (T1CON<6>), must be set to enable this mode.
The timer must be enabled (TON = 1) and the timer
clock source set to internal (TCS = 0).
When the CPU goes into Idle mode, the timer stops
incrementing unless TSIDL = 0. If TSIDL = 1, the timer
resumes the incrementing sequence upon termination
of the CPU Idle mode.
9.2 Timer Prescaler
The input clock (FOSC/4 or external clock) to the 16-bit
Timer has a prescale option of 1:1, 1:8, 1:64 and 1:256,
selected by control bits, TCKPS<1:0> (T1CON<5:4>).
The prescaler counter is cleared when any of the
following occurs:
• A write to the TMR1 register
• A write to the T1CON register
• A device Reset, such as a POR and BOR
However, if the timer is disabled (TON = 0), then the
timer prescaler cannot be reset since the prescaler
clock is halted.
The TMR1 register is not cleared when the T1CON
register is written. It is cleared by writing to the TMR1
register.
9.3 Timer Operation During Sleep Mode
The timer operates during CPU Sleep mode, if:
• The timer module is enabled (TON = 1), and
• The timer clock source is selected as external
(TCS = 1), and
• The TSYNC bit (T1CON<2>) is asserted to a logic
‘0’ which defines the external clock source as
asynchronous.
When all three conditions are true, the timer continues
to count up to the Period register and be reset to
0x0000.
When a match between the timer and the Period
register occurs, an interrupt can be generated if the
respective timer interrupt enable bit is asserted.
9.4 Timer Interrupt
The 16-bit timer has the ability to generate an
interrupt-on-period match. When the timer count
matches the Period register, the T1IF bit is asserted and
an interrupt is generated, if enabled. The T1IF bit must be
cleared in software. The timer interrupt flag, T1IF, is
located in the IFS0 Control register in the interrupt
controller.
When the Gated Time Accumulation mode is enabled,
an interrupt is also generated on the falling edge of the
gate signal (at the end of the accumulation cycle).
Enabling an interrupt is accomplished via the
respective timer interrupt enable bit, T1IE. The timer
interrupt enable bit is located in the IEC0 Control
register in the interrupt controller.
9.5 Real-Time Clock
Timer1, when operating in Real-Time Clock (RTC)
mode, provides time of day and event time-stamping
capabilities. Key operational features of the RTC are:
• Operation from 32 kHz LP oscillator
• 8-bit prescaler
• Low power
• Real-Time Clock interrupts
These operating modes are determined by setting the
appropriate bit(s) in the T1CON register.
FIGURE 9-2:
RECOMMENDED
COMPONENTS FOR
TIMER1 LP OSCILLATOR
RTC
C1
SOSCI
32.768 kHz
XTAL
C2
R
C1 = C2 = 18 pF; R = 100K
dsPIC30FXXXX
SOSCO
9.5.1 RTC OSCILLATOR OPERATION
When the TON = 1, TCS = 1 and TGATE = 0, the timer
increments on the rising edge of the 32 kHz LP oscilla-
tor output signal, up to the value specified in the Period
register and is then reset to ‘0’.
The TSYNC bit must be asserted to a logic ‘0’
(Asynchronous mode) for correct operation.
Enabling the LPOSCEN bit (OSCCON<1>) disables
the normal Timer and Counter modes and enables a
timer carry-out wake-up event.
When the CPU enters Sleep mode, the RTC continues
to operate, provided the 32 kHz external crystal
oscillator is active and the control bits have not been
changed. The TSIDL bit should be cleared to ‘0’ in
order for RTC to continue operation in Idle mode.
9.5.2 RTC INTERRUPTS
When an interrupt event occurs, the respective interrupt
flag, T1IF, is asserted and an interrupt is generated if
enabled. The T1IF bit must be cleared in software. The
respective Timer interrupt flag, T1IF, is located in the
IFS0 register in the interrupt controller.
DS70139G-page 74
© 2010 Microchip Technology Inc.