DSPIC30F2012-30I Datasheet, PDF (118/210 Pages) Microchip Technology – High-Performance, 16-bit Digital Signal Controllers

dsPIC30F2011/2012/3012/3013
16.9 Module Power-Down Modes
The module has two internal power modes.
When the ADON bit is ‘1’, the module is in Active mode;
it is fully powered and functional.
When ADON is ‘0’, the module is in Off mode. The
digital and analog portions of the circuit are disabled for
maximum current savings.
In order to return to the Active mode from Off mode, the
user must wait for the ADC circuitry to stabilize.
16.10 A/D Operation During CPU Sleep
and Idle Modes
16.10.1 A/D OPERATION DURING CPU
SLEEP MODE
When the device enters Sleep mode, all clock sources
to the module are shut down and stay at logic ‘0’.
If Sleep occurs in the middle of a conversion, the
conversion is aborted. The converter will not continue
with a partially completed conversion on exit from
Sleep mode.
Register contents are not affected by the device
entering or leaving Sleep mode.
The ADC module can operate during Sleep mode if the
A/D clock source is set to RC (ADRC = 1). When the
RC clock source is selected, the ADC module waits
one instruction cycle before starting the conversion.
This allows the SLEEP instruction to be executed which
eliminates all digital switching noise from the
conversion. When the conversion is complete, the
CONV bit will be cleared and the result loaded into the
ADCBUF register.
If the A/D interrupt is enabled, the device will wake-up
from Sleep. If the A/D interrupt is not enabled, the ADC
module will then be turned off, although the ADON bit
will remain set.
16.10.2 A/D OPERATION DURING CPU IDLE
MODE
The ADSIDL bit selects if the module will stop on Idle or
continue on Idle. If ADSIDL = 0, the module will
continue operation on assertion of Idle mode. If
ADSIDL = 1, the module will stop on Idle.
16.11 Effects of a Reset
A device Reset forces all registers to their Reset state.
This forces the ADC module to be turned off, and any
conversion and sampling sequence is aborted. The
values that are in the ADCBUF registers are not
modified. The A/D Result register will contain unknown
data after a Power-on Reset.
16.12 Output Formats
The A/D result is 12 bits wide. The data buffer RAM is
also 12 bits wide. The 12-bit data can be read in one of
four different formats. The FORM<1:0> bits select the
format. Each of the output formats translates to a 16-bit
result on the data bus.
FIGURE 16-4:
A/D OUTPUT DATA FORMATS
RAM Contents:
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Read to Bus:
Signed Fractional
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0
Fractional d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0
Signed Integer d11 d11 d11 d11 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Integer
0 0 0 0 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
DS70139G-page 118
© 2010 Microchip Technology Inc.