KSZ8864CNX Datasheet, PDF (7/96 Pages) Microchip Technology – Integrated 4-Port 10/100 Managed Switch with Two MACs MII or RMII Interfaces

KSZ8864CNX/RMNUB
TABLE 2-1: SIGNALS - KSZ8864CNX/RMNUB
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin
Name
RXP1
RXM1
TXP1
TXM1
VDDA12
GND
ISET
VDDAT
RXP2
RXM2
TXP2
TXM2
VDDAT
INTR_N
VDDC
SM3TXEN
SM3TXD3
SM3TXD2
SM3TXD1
SM3TXD0
Type,
Note
2-1
I
I
O
O
P
GND
—
P
I
I
O
O
P
OPU
P
IPD
IPD
IPD
IPD
IPD
21
SM3TXC/
SM3REFCLK
I/O
22
VDDIO
P
23
SM3RXC
I/O
24
SM3RXDV/
SM3CRSDV
IPD/O
Port
1
1
1
1
—
—
—
—
2
2
2
2
—
—
—
3
3
3
3
3
3
—
3
3
Pin Function, Note 2-2
Physical receive signal + (differential)
Physical receive signal – (differential)
Physical transmit signal + (differential)
Physical transmit signal – (differential)
1.2V analog power
Ground with all grounding of die bottom
Set physical transmit output current. Pull-down with a 12.4 kΩ 1%
resistor.
3.3V analog V_DD
Physical receive signal + (differential)
Physical receive signal – (differential)
Physical transmit signal + (differential)
Physical transmit signal – (differential)
3.3V analog V_DD
Interrupt. This pin is the Open-Drain output pin.
1.2V digital core V_DD
MAC3 switch MII/RMII transmit enable
MAC3 switch MII transmit bit 3
MAC3 switch MII transmit bit 2
MAC3 switch MII/RMII transmit bit 1
MAC3 switch MII/RMII transmit bit 0
MAC3 switch MII transmit clock:
Input: SW3-MII MAC mode
Output: SW3-MII PHY mode
Input: SW3-RMII reference clock
3.3V, 2.5V, or 1.8V digital V_DD for digital I/O circuitry
MAC3 switch MII receive clock:
Input: SW3-MII MAC mode
Output: SW3-MII PHY mode
Output: SW3-RMII reference clock
Unused RMII clock can be pull-down or disable by Register 87.
SM3RXDV: MAC3 switch SW3-MII receives data valid.
SM3CRSDV: MAC3 switch SW3-RMII carrier sense/receive data
valid.
 2016 Microchip Technology Inc.
DS00002229A-page 7