KSZ8864CNX Datasheet, PDF (1/96 Pages) Microchip Technology – Integrated 4-Port 10/100 Managed Switch with Two MACs MII or RMII Interfaces

KSZ8864CNX/RMNUB
Integrated 4-Port 10/100 Managed Switch with
Two MACs MII or RMII Interfaces
Features
Advanced Switch Features
• IEEE 802.1q VLAN Support for up to 128 VLAN
Groups (Full-Range 4096 of VLAN IDs)
• Static MAC Table Supports up to 32 Entries
• VLAN ID Tag/Untagged Options, Per Port Basis
• IEEE 802.1p/q Tag Insertion or Removal on a Per
Port Basis Based on Ingress Port (Egress)
• Programmable Rate Limiting at the Ingress and
Egress on a Per Port Basis
• Jitter-Free Per Packet Based Rate Limiting Sup-
port
• Broadcast Storm Protection with Percentage Con-
trol (Global and Per Port Basis)
• IEEE 802.1d Rapid Spanning Tree Protocol RSTP
Support
• Tail Tag Mode (1 Byte Added Before FCS) Sup-
port at Port 4 to Inform the Processor Which
Ingress Port Receives the Packet
• 1.4 Gbps High-Performance Memory Bandwidth
and Shared Memory Based Switch Fabric with
Fully Non-Blocking Configuration
• Dual MII/RMII with MAC 3 SW3-MII/RMII and
MAC 4 SW4-MII/RMII Interfaces
• Enable/Disable Option for Huge Frame Size up to
2000 Bytes Per Frame
• IGMP v1/v2 Snooping (IPv4) Support for Multicast
Packet Filtering
• IPv4/IPv6 QoS Support
• Support Unknown Unicast/Multicast Address and
Unknown VID Packet Filtering
• Self-Address Filtering
Comprehensive Configuration Register Access
• Serial Management Interface (MDC/MDIO) to All
PHYs Registers and SMI Interface (MDC/MDIO)
to All Registers
• High-Speed SPI (up to 25 MHz) and I²C Master
Interface to all Internal Registers
• I/O Pins Strapping and EEPROM to Program
Selective Registers in Unmanaged Switch Mode
• Control Registers Configurable on the Fly (Port-
Priority, 802.1p/d/q, AN…)
QoS/CoS Packet Prioritization Support
• Per Port, 802.1p and DiffServ-Based
• 1/2/4-Queue QoS Prioritization Selection
 2016 Microchip Technology Inc.
• Programmable Weighted Fair Queuing for Ratio
Control
• Re-Mapping of 802.1p Priority Field Per Port
Basis
Integrated 4-Port 10/100 Ethernet Switch
• New Generation Switch with Four MACs and Four
PHYs that are Fully Compliant with the IEEE
802.3u Standard
• Non-Blocking Switch Fabric Ensures Fast Packet
Delivery by Utilizing a 1K MAC Address Lookup
Table and a Store-and-Forward Architecture
• On-Chip 64Kbyte Memory for Frame Buffering
(Not Shared with 1K Unicast Address Table)
• Full-Duplex IEEE 802.3x Flow Control (PAUSE)
with Force Mode Option
• Half-Duplex Back Pressure Flow Control
• HP Auto MDI/MDI-X and IEEE Auto Crossover
Support
• LinkMD^® TDR-Based Cable Diagnostics to Iden-
tify Faulty Copper Cabling
• MII Interface of MAC Supports Both MAC Mode
and PHY Mode
• Per Port LED Indicators for Link, Activity, and 10/
100 Speed
• Register Port Status Support for Link, Activity,
Full-/Half-Duplex and 10/100 Speed
• On-Chip Terminations and Internal Biasing Tech-
nology for Cost Down and Lowest Power Con-
sumption
Switch Monitoring Features
• Port Mirroring/Monitoring/Sniffing: Ingress and/or
Egress Traffic to Any Port or MII/RMII
• MIB Counters for Fully Compliant Statistics Gath-
ering 34 MIB Counters Per Port
• Loopback Support for MAC, PHY, and Remote
Diagnostic of Failure
• Interrupt for the Link Change on Any Ports
Low-Power Dissipation
• Full-Chip Software Power-Down and Per Port
Software Power-Down
• Energy-Detect Mode Support <0.1W Full-Chip
Power Consumption When All Ports Have No
Activity
• Very-Low Full-Chip Power Consumption (~0.3W),
without Extra Power Consumption on Transform-
ers
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