KSZ8864CNX Datasheet, PDF (61/96 Pages) Microchip Technology – Integrated 4-Port 10/100 Managed Switch with Two MACs MII or RMII Interfaces

KSZ8864CNX/RMNUB
TABLE 4-4: ADVANCED CONTROL REGISTER DESCRIPTIONS (CONTINUED)
Address Name
Description
Mode
Port Transmit Packet number for Transmit Queue 1 for low/
6 - 0 Queue 1
high priority packets in four queues mode and
R/W
Ratio[6:0]
high priority packets in two queues mode
Register 181 (0xB5): Reserved
Register 197 (0xC5): Port 1 Control 13
Register 213 (0xD5): Port 2 Control 13
Register 229 (0xE5): Port 3 Control 13
Register 245 (0xF5): Port 4 Control 13
0, strict priority, will transmit all the packets from
7
Enable Port
Transmit Queue
0 Rate
this priority queue 0 before transmit lower prior-
ity queue.
1, bit [6:0] reflect the packet number allow to
transmit from this priority queue 0 within a cer-
R/W
tain time
Port Transmit Packet number for Transmit Queue 0 for lowest
6 - 0 Queue 0
priority packets in four queues mode and low
R/W
Ratio[6:0]
priority packets in two queues mode
Register 182 (0xB6): Reserved
Register 198 (0xC6): Port 1 Rate Limit Control
Register 214 (0xD6): Port 2 Rate Limit Control
Register 230 (0xE6): Port 3 Rate Limit Control
Register 246 (0xF6): Port 4 Rate Limit Control
7 - 5 Reserved
—
RO
4
Ingress Rate
Limit Flow Con-
trol Enable
1 = Flow Control is asserted if the port’s receive
rate is exceeded
0 = Flow Control is not asserted if the port’s
receive rate is exceeded
R/W
3 - 2 Limit Mode
Ingress Limit Mode
These bits determine what kinds of frames are
limited and counted against ingress rate limiting.
= 00, limit and count all frames
= 01, limit and count Broadcast, Multicast, and
R/W
flooded unicast frames
= 10, limit and count Broadcast and Multicast
frames only
= 11, limit and count Broadcast frames only
Count IFG bytes
= 1, each frame’s minimum inter frame gap
1
Count IFG
(IFG) bytes (12 per frame) are included in
R/W
Ingress and Egress rate limiting calculations.
= 0, IFG bytes are not counted.
0
Count Pre
Count Preamble bytes
= 1, Each frame’s preamble bytes (8 per frame)
are included in Ingress and Egress rate limiting
R/W
calculations.
= 0, Preamble bytes are not counted.
Register 183 (0xB7): Reserved
Register 199 (0xC7): Port 1 Priority 0 Ingress Limit Control 1
Register 215 (0xD7): Port 2 Priority 0 Ingress Limit Control 1
Register 231 (0xE7): Port 3 Priority 0 Ingress Limit Control 1
Register 247 (0xF7): Port 4 Priority 0 Ingress Limit Control 1
7
Reserved
—
RO
Default
0000010
1
0000001
000
0
00
0
0
0
 2016 Microchip Technology Inc.
DS00002229A-page 61