KSZ8864CNX Datasheet, PDF (69/96 Pages) Microchip Technology – Integrated 4-Port 10/100 Managed Switch with Two MACs MII or RMII Interfaces

KSZ8864CNX/RMNUB
Then read the indirect data registers bits [38-26] for VID=2 entry:
Read Register 116 (0x74), (Register116 [6:0] are bits 12-6 of VLAN VID=2 entry)
Read Register 117 (0x75), (Register117 [7:2] are bits 5-0 of VLAN VID=2 entry)
2. VLAN Table Write (write the VID=10 entry)
Read the VLAN set that contains VID=8, 9, 10, 11.
Write to Register 110 (0x6E) with 0x14 (read VLAN table selected)
Write to Register 111 (0x6F) with 0x02 (trigger the read operation and VID=8, 9, 10, 11 indirect address)
Read the VLAN set first by the indirect data Registers 114, 115, 116, 117, 118, 119, and 120.
Modify the indirect data registers bits [38-26] by the Register 116 bit [6-0] and Register 117 bit [7-2] as
follows:
Write to Register 116 (0x74), (Register116 [6:0] are bits 12-6 of VLAN VID=10 entry)
Write to Register 117 (0x75), (Register117 [7:2] are bits 5-0 of VLAN VID=10 entry)
Then write the indirect control and address registers:
Write to Register 110 (0x6E) with 0x04 (write VLAN table selected)
Write to Register 111 (0x6F) with 0x02 (trigger the write operation and VID=8, 9, 10, 11 indirect address)
Table 4-10 illustrates the relationship of the indirect address/data registers and VLAN ID.
TABLE 4-10: VLAN ID AND INDIRECT REGISTERS
Indirect Address
High/Low Bit[9-0]
for VLAN Sets
Indirect Data
Register Bits for
Each VLAN Entry
VID Numbers
0
0
0
0
1
1
1
1
2
2
2
2
:
:
:
1023
1023
1023
1023
Bits [12-0]
Bits [25-13]
Bits [38-26]
Bits [51-39]
Bits [12-0]
Bits [25-13]
Bits [38-26]
Bits [51-39]
Bits [12-0]
Bits [25-13]
Bits [38-26]
Bits [51-39]
:
:
:
Bits [12-0]
Bits [25-13]
Bits [38-26]
Bits [51-39]
0
1
2
3
4
5
6
7
8
9
10
11
:
:
:
4092
4093
4094
4095
VID Bit[12-2] in
VLAN Tag
0
0
0
0
1
1
1
1
2
2
2
2
:
:
:
1023
1023
1023
1023
VID Bit[1-0] in VLAN
Tag
0
1
2
3
0
1
2
3
0
1
2
3
:
:
:
0
1
2
3
 2016 Microchip Technology Inc.
DS00002229A-page 69