93AA46AE48 Datasheet, PDF (7/26 Pages) Microchip Technology – 1K Microwire Serial EEPROM with EUI-48™ Node Identity

2.5 Erase All (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle is
identical to the erase cycle, except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS. Clocking of
the CLK pin is not necessary after the device has
entered the ERAL cycle.
FIGURE 2-2:
ERAL TIMING
CS
CLK
93AA46AE48
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL).
VCC must be ≥4.5V for proper operation of ERAL.
Note:
After the ERAL command is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
TCSL
Check Status
DI
1
00
10
x •••
x
DO
High-Z
Note: VCC must be ≥4.5V for proper operation of ERAL.
TSV
Busy
TEC
TCZ
Ready
High Z
 2013-2016 Microchip Technology Inc.
DS20005229C-page 7