93AA46AE48 Datasheet, PDF (10/26 Pages) Microchip Technology – 1K Microwire Serial EEPROM with EUI-48™ Node Identity

93AA46AE48
2.9 Write All (WRAL)
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
For 93AA46AE48, after the last data bit is clocked into
DI, the falling edge of CS initiates the self-timed
auto-erase and programming cycle. Clocking of the
CLK pin is not necessary after the device has entered
the WRAL cycle. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL instruction does not require an ERAL instruction,
but the chip must be in the EWEN status.
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL).
VCC must be 4.5V for proper operation of WRAL.
Note:
After the Write All cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
FIGURE 2-7:
WRAL TIMING
TCSL
CS
CLK
DI
1 0 0 0 1 x ••• x Dx ••• D0
DO
High-Z
Note: VCC must be ≥4.5V for proper operation of WRAL.
TSV
TCZ
Busy
TWL
Ready
HIGH-Z
DS20005229C-page 10
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