93AA46AE48 Datasheet, PDF (12/26 Pages) Microchip Technology – 1K Microwire Serial EEPROM with EUI-48™ Node Identity

93AA46AE48
4.0 PIN DESCRIPTIONS
The description of the pins are listed in Table 4-1.
TABLE 4-1:
Name
CS
CLK
DI
DO
VSS
NC
NC
VCC
PIN FUNCTION TABLE
SOIC
1
2
3
4
5
6
7
8
SOT-23
5
4
3
1
2
—
—
6
Function
Chip Select
Serial Clock
Data In
Data Out
Ground
No Internal Connection
No Internal Connection
Power Supply
4.1 Chip Select (CS)
A high level selects the device; a low level deselects
the device and forces it into Standby mode. However, a
programming cycle that is already in progress will be
completed, regardless of the Chip Select (CS) input
signal. If CS is brought low during a program cycle, the
device will go into Standby mode as soon as the
programming cycle is completed.
CS must be low for 250 ns minimum (TCSL) between
consecutive instructions. If CS is low, the internal
control logic is held in a Reset status.
4.2 Serial Clock (CLK)
The Serial Clock is used to synchronize the
communication between a master device and the
93AA46AE48 series device. Opcodes, address and
data bits are clocked in on the positive edge of CLK.
Data bits are also clocked out on the positive edge of
CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (TCKH) and
clock low time (TCKL). This gives the controlling master
freedom in preparing opcode, address and data.
CLK is a “don't care” if CS is low (device deselected). If
CS is high, but the Start condition has not been
detected (DI = 0), any number of clock cycles can be
received by the device without changing its status
(i.e., waiting for a Start condition).
CLK cycles are not required during the self-timed write
(i.e., auto erase/write) cycle.
After detection of a Start condition, the specified
number of clock cycles (respectively low-to-high
transitions of CLK) must be provided. These clock
cycles are required to clock in all required opcode,
address and data bits before an instruction is executed.
CLK and DI then become “don't care” inputs waiting for
a new Start condition to be detected.
4.3 Data In (DI)
Data In (DI) is used to clock in a Start bit, opcode,
address and data synchronously with the CLK input.
4.4 Data Out (DO)
Data Out (DO) is used in the Read mode to output data
synchronously with the CLK input (TPD after the
positive edge of CLK).
This pin also provides Ready/Busy status information
during erase and write cycles. Ready/Busy status
information is available on the DO pin if CS is brought
high after being low for minimum Chip Select low time
(TCSL) and an erase or write operation has been
initiated.
The Status signal is not available on DO if CS is held
low during the entire erase or write cycle. In this case,
DO is in the High Z mode. If status is checked after the
erase/write cycle, the data line will be high to indicate
the device is ready.
Note:
After a programming cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
DS20005229C-page 12
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