MCP19116 Datasheet, PDF (66/246 Pages) Microchip Technology – Digitally Enhanced Power Analog Synchronous Low-Side PWM Controller with Improved 8k Word Core

MCP19116/7
9.10 Calibration Word 10
Calibration word 10 at memory location 2089h contains
the calibration bits for VREF2 DAC span trim
VR2SPCAL<4:0> and the VREF DAC span trim
VRSPCAL<4:0>. The VR2SPCAL<4:0> is an
individual adjustment specific to calibrating the VREF2
DAC span. Firmware must read these values and copy
them into the VR2SPCAL Special Function Register
located in Bank 2 at 11Ah.
The VRSPCAL<4:0> is an individual adjustment
specific to calibrating the VREF DAC span. Firmware
must read these values and copy them into the
VRSPCAL Special Function Register located in Bank 2
at 119h.
REGISTER 9-10: CALWD10: CALIBRATION WORD 10 REGISTER
U-0
—
bit 13
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
VR2SPCAL4 VR2SPCAL3 VR2SPCAL2 VR2SPCAL1 VR2SPCAL0
bit 8
U-0
—
bit 7
U-0
U-0
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
—
—
VRSPCAL4 VRSPCAL3 VRSPCAL2 VRSPCAL1 VRSPCAL0
bit 0
Legend:
R = Readable bit
-n = Value at POR
P = Programmable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 13
bit 12-8
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
VR2SPCAL<4:0>: VREF2 Span Adjustment bits
Unimplemented: Read as ‘0’
VRSPCAL<4:0>: VREF Span Adjustment bits
DS20005479B-page 66
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