MCP19116 Datasheet, PDF (37/246 Pages) Microchip Technology – Digitally Enhanced Power Analog Synchronous Low-Side PWM Controller with Improved 8k Word Core

MCP19116/7
TABLE 5-6: MCP19116/7 A/D CONVERTER (ADC) CHARACTERISTICS ⁽¹⁾
Electrical Specifications: Unless otherwise noted, operating temperature = -40°C  T_A  +125°C
Param.
No.
Sym.
Characteristic
Min. Typ.^† Max. Units
Conditions
AD01
AD02
AD03
N_R Resolution
E_IL Integral Error ⁽²⁾
E_DL Differential Error ⁽²⁾
AD04 E_OFF Offset Error ⁽²⁾
AD07 E_GN Gain Error ⁽²⁾
AD07 V_AIN Full-Scale Range
—
—
—
—
—
—
—
+3.0
—
2
A_GND
—
10 bits
1
1
+7
6
AV_DD
bit
LSb V_{REF_ADC} = AV_DD
V_{REF_ADC} = V_DD
LSb No missing codes to 10 bits ⁽³⁾
V_{REF_ADC} = AV_DD
V_{REF_ADC} = V_DD
LSb V_{REF_ADC} = AV_DD
V_{REF_ADC} = V_DD
LSb V_{REF_ADC} = AV_DD
V_{REF_ADC} = V_DD
V AV_DD selected as ADC reference
A_GND
—
AD08 Z_AIN Recommended Impedance —
—
of Analog Voltage Source
V_DD
V V_DD selected as ADC reference
10
k
* These parameters are characterized but not tested.
† Data in ‘Typ.’ column is at V_IN = 12V (V_DD = 5V, AV_DD = 4V), 25°C unless otherwise stated. These param-
eters are for design guidance only and are not tested.
Note 1:
2:
When ADC is off, it will not consume any current other than leakage current. The power-down current
specification includes any such leakage from the ADC module. To minimize Sleep current, the ADC refer-
ence must be set to the default AV_DD.
Total Absolute Error includes integral, differential, offset and gain errors.
3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
TABLE 5-7: MCP19116/7 A/D CONVERSION REQUIREMENTS
Electrical Specifications: Unless otherwise noted, operating temperature = -40°C  T_A  +125°C
Param.
No.
Sym.
Characteristic
Min.
Typ.^† Max. Units
Conditions
AD130* T_AD A/D Clock Period 1.6
—
9.0 µs T_OSC-based
A/D Internal RC 1.6
4.0
6.0 µs ADCS<1:0> = 11 (ADRC mode)
Oscillator Period
AD131 T_CNV Conversion Time
—
11
— T_AD Set GO/DONE bit to new data in A/D
(not including
Result registers
Acquisition Time) ⁽¹⁾
AD132* T_ACQ Acquisition Time
—
11.5
— µs
AD133* T_AMP Amplifier Settling
—
—
Time
5
µs
AD134 T_GO Q4 to A/D Clock Start —
T_OSC/2
—
—
† _{Data in ‘Typ.’ column is at VIN = 12V (VDD = 5V, AVDD = 4V), 25°C unless otherwise stated. These parame-}
ters are for design guidance only and are not tested.
* These parameters are characterized but not tested.
Note 1: ADRESH and ADRESL registers may be read on the following T_CY cycle.
 2015-2016 Microchip Technology Inc.
DS20005479B-page 37