MCP19116 Datasheet, PDF (161/246 Pages) Microchip Technology – Digitally Enhanced Power Analog Synchronous Low-Side PWM Controller with Improved 8k Word Core

MCP19116/7
27.0 DUAL CAPTURE/COMPARE (CCD)
MODULE
The CCD module is implemented on the MCP19116/7.
This module is a new module based on the standard
CCP module. It has two capture and compare-only
register sets with no PWM function.
27.1 Capture Mode
In Capture mode, the CCxRH:CCxRL register set
captures the 16-bit value of the TMR1 register when
an event occurs on the DIMI pin. An event is defined
as one of the following:
• Every falling edge
• Every rising edge
• Every 4^th rising edge
• Every 16^th rising edge
The type of event is configured by control bits
CCxM3:CCxM0 (CCDCON<3:0> for register set 1 or
CCDCON<7:4> for register set 2). When a capture is
made, the interrupt request flag bit, CCxIF (PIR1<2>
for register set 1 or PIR1<3> for register set 2), is set.
The interrupt flag must be cleared in software. If
another capture occurs before the value in the register
set is read, the old captured value is overwritten by the
new value.
27.1.1 CCX PIN CONFIGURATION
In Capture mode, the DIMI pin should be configured
as an input by setting the TRIS bit for that pin.
Note: If the CCD pin is configured as an output, a
write to the port can cause a capture
condition.
FIGURE 27-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
Prescaler
÷1, 4, 16
Set Flag bit CCxIF
(PIR1 register)
CCD pin
CCxRH
CCxRL
and
Edge Detect
Capture
Enable
CCDCON<CCxM3:0
System Clock
>
(FOSC)
27.1.2 TIMER1 MODE SELECTION
Timer1 must be running off of the instruction clock for
the CCD module to use the capture feature. If Timer1
is running off of the 8 MHz clock, the capture feature
may not function correctly.
27.1.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
enable for the capture interrupt clear in order to avoid
false interrupts and should clear the flag bit, CCxIF,
following any such change in the operating mode.
TMR1H
TMR1L
27.1.4 CCD PRESCALER
There are four prescaler settings, specified by bits
CCxM3:CCxM0. Whenever the CCD register set is
disabled or not set to Capture mode, the prescaler
counter is cleared. Any reset will clear the prescaler
counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. It is recommended to disable the
register set (CCxM3:0 = 00xx) prior to changing the
prescaler value.
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DS20005479B-page 161