MCP37211-200 Datasheet, PDF (57/142 Pages) Microchip Technology – Power-Saving Modes

MCP37211-200 AND MCP37D11-200
4.8.4.3
Numerically Controlled Oscillator
(NCO)
The on-board Numerically Controlled Oscillator (NCO)
provides the frequency reference for the in-phase and
quadrature mixers in the digital down-converter (DDC).
The NCO serves as a quadrature local oscillator,
capable of producing an NCO frequency of between 0
Hz and f_S with a resolution of f_S/2³², where f_S is the
ADC core sampling frequency.
Figure 4-19 shows the control signals associated with
the NCO. In octal- or dual-channel mode, the NCO
allows the output phase to be adjusted on a
per-channel basis.
Note: The NCO is only used for DDC or CW octal-
channel mode. It should be disabled when
not in use.
CH(n) NCO_PHASE<15:0> Phase Offset Control
Phase Dither
EN_PHSDITH
EN_LFSR
Amplitude Dither
EN_AMPDITH
EN_LFSR
EN_NCO NCO Tuning
NCO_TUNE<31:0>
FIGURE 4-19:
NCO block diagram
• NCO Frequency Control:
The NCO frequency is programmed from 0 Hz to f_S,
using the 32-bit-wide unsigned register variable
NCO_TUNE<31:0> in Addresses 0x82 – 0x85
(Registers 5-43 – 5-46).
The following equation is used to set the
NCO_TUNE<31:0> register:
EQUATION 4-7: NCO FREQUENCY
NCO_TUNE<31:0>=
Where:
ro
u
nd


2³²

M------o---d----_{--f--fN-S--C----O---}_---f--S---
f_S = sampling frequency (Hz)
f_NCO = desired NCO frequency (Hz)
Mod (f_NCO, f_S) = gives the remainder of f_NCO/f_S
Mod() is a remainder function. For
Mod(5,2) = 1 and Mod(1.999, 2) = 1.999.
Example 1:
If f_NCO is 100 MHz and f_S is 200 MHz:
example,
ModfNCO fS = Mod100 200= 100
NCO_TUNE<31:0>= round_232  ^{M------o---d----}--₂₁---₀₀---₀₀---^---²---⁰---⁰----^{}
= 0x8000 0000
Example 2:
If f_NCO is 199.99999994 MHz and f_S is 200 MHz:
ModfNCO fS = Mod199.99999994 200= 199.99999994
NCO_TUNE<31:0>= round_232  -M-----o---d----^--¹---⁹---⁹---^.--⁹--₂-⁹--₀-⁹--₀-⁹---⁹---⁹---⁹---⁴---^---²---⁰---⁰----^{}
= 0xFFFF FFFF
Sine/Cosine
Signal Generator
NCO Output
4.8.4.4 NCO Amplitude and Phase Dither
The EN_AMPDITH and EN_PHSDITH parameters in
Address 0x80 (Register 5-41) can be used for
amplitude and phase dithering, respectively. In
principle, these will dither the quantization error created
by the use of digital circuits in the mixer and local
oscillator, thus reducing spurs at the expense of noise.
In practice, the DDC circuitry has been designed with
sufficient noise and spurious performance for most
applications. In the worst-case scenario, the NCO has
an SFDR of greater than 116 dB when the amplitude
dither is enabled, and 112 dB when disabled. Although
the SNR (≈ 93 dB) of the DDC is not significantly
affected by the dithering option, using the NCO with
dithering options enabled is always recommended for
the best performance.
4.8.4.5
NCO for f_S/8 and f_S/(8xDER)
The output of the first down-conversion block (DDC1)
is a complex signal (comprising I and Q data) which can
then be optionally decimated further up to 128x to
provide both a lower output data rate and input channel
filtering. If f_S/8 mode is enabled, a second mixer stage
(DDC2) will convert the I/Q signals to a real signal
centered at half of the current Nyquist frequency; i.e., if
the output data rate in I/Q mode is 25 Msps per channel
(12.5 MHz Nyquist), then in f_S/8 mode the output data
rate would be 50 Msps (25 Msps each for I and Q), and
the signal would be re-centered around 12.5 MHz. In
single-channel mode, this is done at the output of the
decimation filters (if used). In dual-channel mode, this
must be done prior to the decimation.
When decimation is enabled, the I/Q outputs are up-
converted by f_S/(8xDER), where DER is the additional
decimation rate added by the FIR decimation filters.
This provides a decimated output signal centered at
f_S/8 or f_S/(8xDER) in the frequency domain.
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DS20005355C-page 57