MCP37211-200 Datasheet, PDF (53/142 Pages) Microchip Technology – Power-Saving Modes

MCP37211-200 AND MCP37D11-200
4.8.3 DECIMATION FILTERS
The decimation feature is available in single and dual-
channel modes and CW octal-channel mode.
Figure 4-16 shows a simplified decimation filter block,
and Table 4-16 shows the register settings. The
decimation rate is controlled by FIR_A<8:0> and
FIR_B<7:0> register settings (Addresses 0x7A –
0x7C: Registers 5-35 - 5-37). These registers are
thermometer encoded.
In single-channel mode, FIR B is disabled and only
FIR A is used. In this mode, the maximum program-
mable decimation rate is 512x using nine cascaded
decimation stages.
In dual-channel mode or when using the Digital Down-
Conversion (DDC) in I/Q mode, both FIR A and FIR B
are used (see Figure 4-16). In this case, both channels
are set to the same decimation rate. Note that stage
1A in FIR A is unused: the user must clear FIR_A<0>
in Address 0x7A (Register 5-35). In dual-channel
mode, the maximum programmable decimation rate is
up to 256x, which is half the single-channel decimation
rate (512x).
The overall SNR performance can be improved with
higher decimation rate, but limited to about 73.7 dBFS
after 16x. This limitation is mainly due to the relative
quantization noise level with respect to the 12-bit LSB
size. Decimation rates beyond 16x do not further improve
SNR but do serve to filter the output data and reduce the
overall output data rate. Table 4-15 summarizes decima-
tion rate versus SNR.
TABLE 4-15: DECIMATION RATE VS. SNR
PERFORMANCE
Decimation Rate
SNR (dBFS)
2x
71.4
4x
72.2
8x
72.9
16x
73.3
32x
64x
128x
73.7
256x
512x
Note: The above data is validated with
f_S = 200 Msps, f_IN = 5 MHz, A_IN = -1 dBFS.
4.8.3.1
Output Data Rate and Clock Phase
Control When Decimation is Used
When decimation is used, it also reduces the output
clock rate and output bandwidth by a factor equal to
the decimation rate applied: the output clock rate is
therefore no longer equal to the ADC sampling clock.
The user needs to adjust the output clock and data
rates in Address 0x02 (Register 5-3) based on the
decimation applied. This allows the output data to be
synchronized to the output data clock.
Phase shifts in the output clock can be achieved using
DCLK_PHDLY_DEC<2:0> in Address 0x64
(Register 5-22). Only four output sampling phases are
available when a decimation rate of 2x is used, while
all eight clock phases are available for other
decimation rates. See Section 4.12.8 “Output Data
and Clock Rates” for more details.
4.8.3.2
Using Decimation with CW
Beamforming and Digital Down-
Conversion
Decimation can be used in conjunction with CW octal-
channel mode or DDC. In CW octal-channel mode
operation, the eight input channels are summed into a
single channel prior to entering the decimation filters.
When DDC is enabled, the I and Q outputs can be
decimated using the same signal path for the dual-
channel mode: I and Q data are fed into Channel A
and B, respectively.
In DDC mode, the half-band filter already includes a
2x decimation rate. Therefore, the maximum
decimation rate setting for I/Q filtering is 128x for the
FIR_A<8:1> and FIR_B<7:0>. See Section 4.8.4
“Digital Down-Conversion (MCP37D11-200 only)”
for details.
Note:
Fractional Delay Recovery, Digital
Gain/Offset adjustment and DDC for I/Q
data options occur prior to the decimation
filters if they are enabled.
 2014-2016 Microchip Technology Inc.
DS20005355C-page 53