MCP37211-200 Datasheet, PDF (46/142 Pages) Microchip Technology – Power-Saving Modes

MCP37211-200 AND MCP37D11-200
4.7.2 USING PLL MODE
The PLL block is mainly used when clock multiplication
is needed. When CLK_SOURCE = 1, the sampling
frequency (f_S) of the ADC core is coming from the
internal PLL block.
The recommended PLL output clock range is from
80 MHz to 250 MHz. The external clock input is used
as the PLL reference frequency. The range of the clock
input frequency is from 5 MHz to 250 MHz.
Note:
The PLL mode is only supported for
sampling frequencies between 80 MHz
and 250 MHz.
4.7.2.1
PLL Output Frequency and Output
Control Parameters
The internal PLL can provide a stable timing output
ranging from 80 MHz to 250 MHz. Figure 4-11 shows the
PLL block using a charge-pump-based integer N PLL
and the PLL output control block. The PLL block
includes various user control parameters for the desired
output frequency. Table 4-6 summarizes the PLL control
register bits and Table 4-7 shows an example of register
bit settings for the PLL charge pump and loop filter.
The PLL block consists of:
• Reference Frequency Divider (R)
• Prescaler - which is a feedback divider (N)
• Phase/Frequency Detector (PFD)
• Current Charge Pump
• Loop Filter - a 3^rd order RC low-pass filter
• Voltage-Controlled Oscillator (VCO)
The external clock at the CLK+ and CLK- pins is the
input frequency to the PLL. The range of input fre-
quency (f_REF) is from 5 MHz to 250 MHz. This input
frequency is divided by the reference frequency
divider (R) which is controlled by the 10-bit-wide
PLL_REFDIV<9:0> setting. In the feedback loop, the
VCO frequency is divided by the prescaler (N) using
PLL_PRE<11:0>.
The ADC core sampling frequency (f_S), ranging from
80 MHz to 250 MHz, is obtained after the output
frequency divider (PLL_OUTDIV<3:0>). For stable
operation, the user needs to configure the PLL with
the following limits:
• Input clock frequency (f_REF)
• Charge pump input frequency
(after PLL reference divider)
= 5 MHz to 250 MHz
= 4 MHz to 50 MHz
• VCO output frequency
• PLL output frequency after
output divider
= 1.075 to1.325 GHz
= 80 MHz to 250 MHz
The charge pump is controlled by the PFD, and forces
sink (DOWN) or source (UP) current pulses onto the
loop filter. The charge pump bias current is controlled
by the PLL_CHAGPUMP<3:0> bits, approximately
25 µA per step. The loop filter consists of a 3^rd order
passive RC filter. Table 4-7 shows the recommended
settings of the charge pump and loop filter parameters,
depending on the charge pump input frequency range
(output of the reference frequency divider).
When the PLL is locked, it tracks the input frequency
(f_REF) with the ratio of dividers (N/R). The PLL operat-
ing status is monitored by the PLL status indication bits:
<PLL_VCOL_STAT> and <PLL_VCOH_STAT> in
Address 0xD1 (Register 5-81).
Equation 4-3 shows the VCO output frequency (f_VCO) as
a function of the two dividers and reference frequency:
EQUATION 4-3: VCO OUTPUT
FREQUENCY
f_VCO
=


N-R--_
f_RE
F
=
1.075
GHz
to
1.325
GHz
Where:
N = 1 to 4095 controlled by PLL_PRE<11:0>
R = 1 to 1023 controlled by PLL_REFDIV<9:0>
See Addresses 0x54 to 0x57 (Registers 5-9 – 5-12) for
these bits settings.
The tuning range of the VCO is 1.075 GHz to
1.325 GHz. N and R values must be chosen so the
VCO is within this range. In general, lower values of the
VCO frequency (f_VCO) and higher values of the charge
pump frequency (f_Q) should be chosen to optimize the
clock jitter. Once the VCO output frequency is
determined to be within this range, set the final ADC
sampling frequency (f_S) with the PLL output divider
using PLL_OUTDIV<3:0>. Equation 4-4 shows how to
obtain the ADC core sampling frequency:
EQUATION 4-4: SAMPLING FREQUENCY
f_S
=


P-----L---L----_--f-O-^{V---C-U--O---T---D-----I--V-- }
=
80
MHz to 250 MHz
Table 4-8 shows an example of generating
f_S = 200 MHz output using the PLL control parameters.
4.7.2.2 PLL Calibration
The PLL should be recalibrated following a change in
clock input frequency or in the PLL Configuration
register bit settings (Addresses 0x54 - 0x57;
Registers 5-9 – 5-12).
The PLL can be calibrated by toggling the PLL_-
CAL_TRIG bit in Address 0x6B (Register 5-27) or by
sending a SOFT_RESET command (See Address
0x00, Register 5-1). The PLL calibration status is
observed by the PLL_CAL_STAT bit in Address 0xD1
(Register 5-81).
4.7.2.3
Monitoring of PLL Drifts
The PLL drifts can be monitored using the status mon-
itoring bits in Address 0xD1 (Register 5-81). Under
normal operation, the PLL maintains a lock across all
temperature ranges. It is not necessary to actively
monitor the PLL unless extreme variations in the sup-
ply voltage are expected or if the input reference clock
frequency has been changed.
DS20005355C-page 46
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