DSPIC33EPXXX806 Datasheet, PDF (457/614 Pages) Microchip Technology – 16-bit Microcontrollers and Digital Signal Controllers (up to 512 KB Flash and 52 KB SRAM) with High-Speed PWM, USB, and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
27.0 PROGRAMMABLE CYCLIC
REDUNDANCY CHECK (CRC)
GENERATOR
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXX(GP/MC/MU)806/
810/814 and PIC24EPXXX(GP/GU)810/
814 families of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 27. “Pro-
grammable Cyclic Redundancy Check
(CRC)” (DS70346) of the “dsPIC33E/
PIC24E Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The programmable CRC generator offers the following
features:
• User-programmable (up to 32nd order)
polynomial CRC equation
• Interrupt output
• Data FIFO
The programmable CRC generator provides a
hardware-implemented method of quickly generating
checksums for various networking and security
applications. It offers the following features:
• User-programmable CRC polynomial equation,
up to 32 bits
• Programmable shift direction (little or big-endian)
• Independent data and polynomial lengths
• Configurable Interrupt output
• Data FIFO
A simplified block diagram of the CRC generator is
shown in Figure 27-1. A simple version of the CRC shift
engine is shown in Figure 27-2.
FIGURE 27-1:
CRC BLOCK DIAGRAM
CRCDATH
CRCDATL
2 * FP Shift Clock
Variable FIFO
(4x32, 8x16 or 16x8)
FIFO Empty Event
Shift Buffer
0 1 LENDIAN
CRCISEL
1
Set CRCIF
0
CRC Shift Engine
Shift Complete Event
FIGURE 27-2:
Shift Buffer
Data
CRCWDATH CRCWDATL
CRC SHIFT ENGINE DETAIL
CRCWDATH
Read/Write Bus
X(1)⁽¹⁾
X(2)⁽¹⁾
Bit 0
Bit 1
Bit 2
CRCWDATL
X(n)⁽¹⁾
Bit n⁽²⁾
Note 1: Each XOR stage of the shift engine is programmable. See text for details.
2: Polynomial length n is determined by ([PLEN<4:0>] + 1).
© 2009-2012 Microchip Technology Inc.
Preliminary
DS70616F-page 457