DSPIC33EPXXX806 Datasheet, PDF (449/614 Pages) Microchip Technology – 16-bit Microcontrollers and Digital Signal Controllers (up to 512 KB Flash and 52 KB SRAM) with High-Speed PWM, USB, and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
26.3 RTCC Registers
REGISTER 26-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION
REGISTER⁽¹⁾
R/W-0
RTCEN⁽²⁾
bit 15
U-0
R/W-0
R-0
R-0
R/W-0
—
RTCWREN RTCSYNC HALFSEC⁽³⁾ RTCOE
R/W-0
R/W-0
RTCPTR<1:0>
bit 8
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
CAL<7:0>
R/W-0
R/W-0
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9-8
RTCEN: RTCC Enable bit⁽²⁾
1 = RTCC module is enabled
0 = RTCC module is disabled
Unimplemented: Read as ‘0’
RTCWREN: RTCC Value Registers Write Enable bit
1 = RTCVAL register can be written to by the user application
0 = RTCVAL register is locked out from being written to by the user application
RTCSYNC: RTCC Value Registers Read Synchronization bit
1 = A rollover is about to occur in 32 clock edges (approximately 1 ms)
0 = A rollover will not occur
HALFSEC: Half-Second Status bit⁽³⁾
1 = Second half period of a second
0 = First half period of a second
RTCOE: RTCC Output Enable bit
1 = RTCC output is enabled
0 = RTCC output is disabled
RTCPTR<1:0>: RTCC Value Register Pointer bits
Points to the corresponding RTCC Value register when reading the RTCVAL register; the
RTCPTR<1:0> value decrements on every access of the RTCVAL register until it reaches ‘00’.
Note 1: The RCFGCAL register is only affected by a POR.
2: A write to the RTCEN bit is only allowed when RTCWREN = 1.
3: This bit is read-only. It is cleared when the lower half of the MINSEC register is written.
© 2009-2012 Microchip Technology Inc.
Preliminary
DS70616F-page 449