SIO1007 Datasheet, PDF (39/108 Pages) Microchip Technology – LPC Super I/O LPC IrDA Hot Docking Chip with UART

SIO1007
10.4.4 GENERATING CIRCC2 INTERRUPT EVENTS
The CIRCC2 block generates two types of interrupt events: a wake event and a runtime event.
The wake event, if enabled, can be used to generate a PME event to wake the system. The CIRCC2 block can be used
to generate a wake event for an NEC PPM and RC5 event. To generate a wake event, the CIRCC2 block must first be
powered and enabled (see CIRCC2 Operational Power States on page 38). The CIR mode, NEC PPM and RC5, is
configured directly in the SCE registers. The PME event is reported in bit[1] of the PME_STS2 register at offset 03h of
the Runtime Register block. This status event can be used to generate a PME interrupt if bit[2] of the PME_EN2 register
is enabled and PMEs are enabled in the PME_EN register at offset 01h. See Section 17.0, "Runtime Registers," on
page 53.
The runtime event (if enabled) may be reported as an SMI event or a Serial IRQ event. The following diagram shows
the interrupt event (INT) that is used to generate a runtime event. To have a runtime event, the individual status events
must be enabled. In addition to the individual interrupt enables, the Master Interrupt Enable located in the SCE Master
Block Control Register must also be enabled. These interrupt status and enable bits are defined in the Consumer Infra-
red Communications Controller 2 (CIRCC2) specification. If a runtime event occurs bit[3] of the SMI_STS2 register at
offset 09h of the Runtime register block will be set. If bit[3] of the SMI_EN2 register is one and if SMI’s are enabled on
the IO_SMI# pin an SMI event will be generated.
This runtime event can also be routed to the Serial IRQs. To enable Serial IRQs for the CIRCC2 runtime events software
must select an IRQ channel in the CIRCC2 IRQ/DMA Select register. See CR18 on page 68.
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