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EVB-LAN9353 Datasheet, PDF (38/43 Pages) Microchip Technology – EVB-LAN9353 Evaluation Board User’s Guide
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FIGURE B-9:
EVB-LAN9353 EVALUATION BOARD SCHEMATIC 9
MII Male for External MAC Board
AMP - 6-5174218-2
MII_RA
10uF C59
5V
0.1uF C61
P0_MDIO
P0_MDC
P0_OUTD3
P0_OUTD2
P0_OUTD1_MODE2
P0_OUTD0_MODE1
P0_OUTDV
P0_OUT/REF_CLK_MODE0
P0_OUTER_SPEED
P0_INER
P0_INCLK
P0_INDV
P0_IND0
P0_IND1
P0_IND2
P0_IND3
P0_COL
P0_CRS
J23
R126
R127
0E MAC_TXCLK0
0E MAC_RXCLK0
1
2 +5V[3]
3 MDIO
4 MDC
5 RXD3
6 RXD2
7 RXD1
8 RXD0
9 RX_DV
10 RX_CLK
11 RX_ER
12 TX_ER
13 TX_CLK
14 TX_EN
15 TXD0
16 TXD1
17 TXD2
18 TXD3
19 COL
20 CRS
+5V[4]
PORT 0
40
+5V[1] 39
COMMON[1] 38
COMMON[2] 37
COMMON[3] 36
COMMON[4] 35
COMMON[5] 34
COMMON[6] 33
COMMON[7] 32
COMMON[8] 31
COMMON[9] 30
COMMON[10] 29
COMMON[11] 28
COMMON[12] 27
COMMON[13] 26
COMMON[14] 25
COMMON[15] 24
COMMON[16] 23
COMMON[17] 22
COMMON[18] 21
+5V[2]
MII Female for External PHY Board 5V
FEMALE MII CONN
AMP - 749069-4
C60 10uF
C62 0.1uF
J24
P0_INCLK
R128
P0_OUTER_SPEED DNP R129
P0_OUT/REF_CLK_MODE0 R130
P0_MDIO
P0_MDC
P0_IND3
P0_IND2
P0_IND1
P0_IND0
P0_INDV
0E PHY_RXCLK0
P0_INER
0E TXER0
0E PHY_TXCLK0
P0_OUTDV
P0_OUTD0_MODE1
P0_OUTD1_MODE2
P0_OUTD2
P0_OUTD3
P0_COL
P0_CRS
1 21
2 22
3 23
4 24
5 25
6 26
7 27
8 28
9 29
10 30
11 31
12 32
13 33
14 34
15 35
16 36
17 37
18 38
19 39
20 40
Port 0 - RMII RX Clock Configurations
SW23
2 MAC_RXCLK0
MAC_TXCLK0 1
3 Default Short 2-3
JS102011CQN
SW24
2 PHY_RXCLK0
PHY_TXCLK0 1
3 Default (1-3)
JS102011CQN
Switch
Settings
Description
Mode
SW23 (1-3) TX Clock used as a Reference Clock
Default
RMII MAC
SW23 (1-2) RX Clock used as a Reference Clock RMII MAC
SW24 (1-3) Reference clock used as a TX clock
Default
SW24 (1-2) Reference clock used as a RX clock
RMII PHY
RMII PHY
Note: 1. For Switches to short 1-3, Knob Position should be
at 1-2 and vice versa .
2. External PHY considered LAN8742
PORT 1
MII Male for External MAC Board
AMP - 6-5174218-2
MII_RA
10uF C63
5V
0.1uF C64
J18
P1_MDIO_SPEED
P1_MDC_DUPLEX
P1_OUTD1_MODE2
P1_OUTD0_MODE1
P1_OUTDV
P1_REFCLK_MODE0
P1_INDV
P1_IND0
P1_IND1
1
2 +5V[3]
3 MDIO
4 MDC
5 RXD3
6 RXD2
7 RXD1
8 RXD0
R135 0E MAC_TXCLK1 9 RX_DV
10 RX_CLK
11 RX_ER
MAC_RXCLK1 12 TX_ER
13 TX_CLK
14 TX_EN
15 TXD0
16 TXD1
17 TXD2
18 TXD3
P1_CRS
19 COL
20 CRS
+5V[4]
P1_INDV
P1_CRS
For RMII
40
+5V[1] 39
COMMON[1] 38
COMMON[2] 37
COMMON[3] 36
COMMON[4] 35
COMMON[5] 34
COMMON[6] 33
COMMON[7] 32
COMMON[8] 31
COMMON[9] 30
COMMON[10] 29
COMMON[11] 28
COMMON[12] 27
COMMON[13] 26
COMMON[14] 25
COMMON[15] 24
COMMON[16] 23
COMMON[17] 22
COMMON[18] 21
+5V[2]
MII Female for External PHY Board 5V
FEMALE MII CONN
AMP - 749069-4
C65 10uF
C66 0.1uF
J19
P1_MDIO_SPEED
P1_MDC_DUPLEX
P1_IND1
P1_IND0
P1_INDV
PHY_TXCLK1
P1_REFCLK_MODE0
R136 0E PHY_RXCLK1
P1_OUTDV
P1_OUTD0_MODE1
P1_OUTD1_MODE2
P1_CRS
1 21
2 22
3 23
4 24
5 25
6 26
7 27
8 28
9 29
10 30
11 31
12 32
13 33
14 34
15 35
16 36
17 37
18 38
19 39
20 40
Port 1 - RMII RX Clock Configurations
SW25
2 MAC_RXCLK1
MAC_TXCLK1 1
3 Default Short 2-3
JS102011CQN
SW26
2 PHY_RXCLK1
PHY_TXCLK1 1
3 Default (1-3)
JS102011CQN
Switch
Settings
Description
Mode
SW25 (1-3) TX Clock used as a Reference Clock
Default
RMII MAC
SW25 (1-2) RX Clock used as a Reference Clock RMII MAC
SW26 (1-3) Reference clock used as a TX clock
Default
SW26 (1-2) Reference clock used as a RX clock
RMII PHY
RMII PHY
Note: 1. For Switches to short 1-3, Knob Position should be
at 1-2 and vice versa .
2. External PHY considered LAN8742
J28 = Default open
Short for RMII mode
J25
P0_INDV 1
2 P0_CRS
Short option for RXDV & CRS
for RMII mode
Pullup for MDIO(common for all PHY) signal
TP7 TP8
3V3
P1_MDIO_SPEED
P1_MDC_DUPLEX
1.5K
10K
R137
R138
Pullup for MDIO(common for all PHY) signal
TP5 TP6
3V3
J26 = Default open
P0_MDIO
2
P0_MDC
1 1.5K
J26
10K
R131
R132 DNP
3V3
R133
3V3
R139
R134
10K P0_OUTDV
10K P1_OUTDV
49.9K TXER0
DNP
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