EVB-LAN9353 Datasheet, PDF (36/43 Pages) Microchip Technology – EVB-LAN9353 Evaluation Board User’s Guide

FIGURE B-7:
EVB-LAN9353 EVALUATION BOARD SCHEMATIC 7
3V3
3V3
P0_OUT/REF_CLK_MODE0 _R104
SW5
10.0K ₁
2
3
JS102011CQN
P0_MODE0
3V3
P1_REFCLK_MODE0/P0_INCLK
R105
SW6
10.0K
1
2
3
JS102011CQN
P1_MODE0
3V3
Config 10
Port 0 : External (MII/RMII/TMII)
Port 1 and Port 2 : Internal
P0_OUTD0_MODE1 R106
SW7
10.0K
1
2
3
JS102011CQN
P0_MODE1 ^{P1_OUTD0_MODE1/P0_OUTD2_MODE3}
R107
10.0K
SW8
2
1
3
JS102011CQN
WŽƌƚ ϬDK^dZ WDĂƉƉŝŶŐ
P0_MODE3 & _{Wϭͺ/EdW,z͗ WϬͺDKϯ WϬͺDKϮ WϬͺDKϭ WϬͺDKϬ}
P1_MODE1
:ϱĂŶĚ:ϴ ^tϴ
^tϵ
^tϳ
^tϱ
DK
P0_OUTD1_MODE2 _R108
SW9
10.0K
1
2
3
3V3
P0_MODE2
JS102011CQN
P1_OUTD1_MODE2/P0_OUTD3
R109
3V3
SW10
10.0K ₁
2
3
JS102011CQN
P1_MODE2
Note: For Switches to short 1-3, Knob Position should be at 1-2 and vice versa .
Note: CONFIG9 or CONFIG 10 must be configured before P0/P1 mode configurations
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dž
E
dž
E
Ϭ
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D// D 
D// W,z
dƵƌďŽ D// W,zϭϮ ŵĂ
dƵƌďŽ D// W,zϭϲ ŵĂ
Config 9 :
Port 0 and Port 1 : External (RMII) and
Port 2 : Internal
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dž
E
Ϭ
^ŚŽƌƚ ϭͲϯ
ZD// D  ĐůŽĐŬ ŝŶ
ZD// D  ĐůŽĐŬ ŽƵƚϭϮŵĂ
Wϭͺ/EdW,z ͗
:ϱ ĂŶĚ :ϴ
Ϭ
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^ŚŽƌƚ ϮͲϯ
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^ŚŽƌƚ ϮͲϯ
Ϭ
^ŚŽƌƚ ϮͲϯ
WŽƌƚϭ ;ZD//Ϳ DK ^dZ W DĂƉƉŝŶŐ
WϭͺDKϮ WϭͺDKϭ WϭͺDKϬ
WŽƌƚ ϭ DŽĚĞ
^tϭϬ
^tÏ´
^tϲ
Ϭ
Ϭ
dž
ZD// D  ĐůŽĐŬ ŝŶ
^ŚŽƌƚ ϭͲϯ ^ŚŽƌƚ ϭͲϯ
ŽƉĞŶ
;ZD// ƉŝŶ ƌĞŵĂƉ ŵŽĚĞͿ
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^ŚŽƌƚ ϭͲϮ
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ZD// D  ĐůŽĐŬ ŽƵƚ ϭϮŵĂ
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ZD// D  ĐůŽĐŬ ŽƵƚ ϭϲŵĂ
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Ϭ
^ŚŽƌƚ ϭͲϯ
dž
ŽƉĞŶ
ZD// W,z ĐůŽĐŬ ŝŶ
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^ŚŽƌƚ ϭͲϮ
dž
E
Ϭ
^ŚŽƌƚ ϭͲϯ
Ž
ZD// D  ĐůŽĐŬ ŽƵƚϭϲŵĂ
ZD// W,zĐůŽĐŬ ŝŶ
ZD// W,zĐůŽĐŬ ŽƵƚ ϭϮŵĂ
ZD// W,zĐůŽĐŬ ŽƵƚ ϭϲŵĂ
Ϭ
^ŚŽƌƚ ϮͲϯ
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^ŚŽƌƚ ϭͲϮ
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^ŚŽƌƚ ϭͲϮ
Ϭ
^ŚŽƌƚ ϭͲϯ
ZD// W,z ĐůŽĐŬ ŽƵƚ ϭϮŵĂ
Ϭ
^ŚŽƌƚ ϮͲϯ
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^ŚŽƌƚ ϭͲϮ
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^ŚŽƌƚ ϭͲϮ
dž
ŽƉĞŶ
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^ŚŽƌƚ ϭͲϮ
dž
ŽƉĞŶ
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^ŚŽƌƚ ϭͲϮ
dž
ŽƉĞŶ
ZD// W,z ĐůŽĐŬ ŽƵƚ ϭϲŵĂ
/ŶƚĞƌŶĂů W,z
P1_REFCLK_MODE0/P0_INCLK
P1_OUTD1_MODE2/P0_OUTD3
P1_OUTD0_MODE1/P0_OUTD2_MODE3
P0_OUTD1_MODE2
P0_OUTD0_MODE1
P0_OUT/REF_CLK_MODE0