EVB-LAN9353 Datasheet, PDF (22/43 Pages) Microchip Technology – EVB-LAN9353 Evaluation Board User’s Guide

EVB-LAN9353 Evaluation Board User’s Guide
The “duplex_strap_1” strap from J30 is used to determine the link partners duplex abil-
ity when in Port 1 RMII MAC mode as shown below in Table 10.
The “speed_strap_1” strap from J31 is used to determine the link partners speed ability
and to determine the parallel detect speed when in Port 1 “RMII MAC” mode as shown
below in Table 3-11.
TABLE 3-11: EMULATED LINK PARTNER DEFAULT ADVERTISED ABILITY
FOR PORT 1
J30
(P1_DUPLEX)
J31 (P1_SPEED) duplex_strap_1
speed_strap_1
ADVERTISED
LINK PARTNER
ABILITY
1-2
2-3
1
0
10BASE-T
full-duplex
(0010)
1-2
1-2
1
1
100BASE-X
full-duplex
(1000)
2-3
2-3
0
0
10BASE-T
half-duplex
(0001)
2-3
1-2
0
1
100BASE-X
half-duplex
(0100)
Note: For Switches to short 1-3, Knob Position should be at 1-2 and vice versa.
3.1.5 Port 0/Port 1 Mode Configurations
CONFIG 9 or CONFIG 10 must be configured before P0/P1 mode configurations. For
a detailed jumper settings for CONFIG 9 or CONFIG 10 refer to section 3.1.3
P0 Mode configuration straps (SW5, SW6, SW7 & SW8) are used to configure the
hard-straps such as Switch Port 0 Mode Strap (P0_mode_strap[1:0]), Switch Port 0
RMII Clock Direction Strap (P0_rmii_clock_dir_strap) and Switch Port 0 Clock Strength
Strap (P0_clock_strength_strap) as shown below in Table 3-12.
TABLE 3-12: PORT 0 MODE STRAP MAPPING
P1_
INTPHY
(J5 & J8)
P0_MODE3 P0_MODE2 P0_MODE1 P0_MODE0
(SW8)
(SW9)
(SW7)
(SW5)
MODE
1-2
1-3
1-3
X
X
MII MAC
1-2
1-3
1-2
1-3
X
MII PHY
1-2
1-3
1-2
1-2
1-3
Turbo MII PHY 12 ma
1-2
1-3
1-2
1-2
1-2
Turbo MII PHY 16 ma
2-3
X
1-3
1-3
1-2
1-2
X
RMII MAC clock in
(default)
2-3
X
1-3
1-2
1-3
RMII MAC clock out
1-2
1-2
12ma
2-3
X
1-3
1-2
1-2
RMII MAC clock out
1-2
1-2
16ma
2-3
X
1-2
1-3
X
RMII PHY clock in
1-2
1-2
DS50002393A-page 22
 2015 Microchip Technology Inc.