DSPIC30F5013-20I Datasheet, PDF (38/220 Pages) Microchip Technology – 16-bit Digital Signal Controllers

dsPIC30F5011/5013
Address Error Trap:
This trap is initiated when any of the following
circumstances occurs:
• A misaligned data word access is attempted
• A data fetch from an unimplemented data memory
location is attempted
• A data access of an unimplemented program
memory location is attempted
• An instruction fetch from vector space is
attempted
Note:
In the MAC class of instructions, wherein
the data space is split into X and Y data
space, unimplemented X space includes
all of Y space, and unimplemented Y
space includes all of X space.
• Execution of a “BRA #literal” instruction or a
“GOTO #literal” instruction, where literal is
an unimplemented program memory address
• Executing instructions after modifying the PC to
point to unimplemented program memory
addresses. The PC may be modified by loading a
value into the stack and executing a RETURN
instruction.
Stack Error Trap:
This trap is initiated under the following conditions:
• The Stack Pointer is loaded with a value that is
greater than the (user programmable) limit value
written into the SPLIM register (stack overflow)
• The Stack Pointer is loaded with a value that is
less than 0x0800 (simple stack underflow)
Oscillator Fail Trap:
This trap is initiated if the external oscillator fails and
operation becomes reliant on an internal RC backup.
4.3.2 HARD AND SOFT TRAPS
It is possible that multiple traps can become active
within the same cycle (e.g., a misaligned word stack
write to an overflowed address). In such a case, the
fixed priority shown in Figure 4-2 is implemented,
which may require the user to check if other traps are
pending, in order to completely correct the fault.
‘Soft’ traps include exceptions of priority level 8 through
level 11, inclusive. The arithmetic error trap (level 11)
falls into this category of traps.
‘Hard’ traps include exceptions of priority level 12
through level 15, inclusive. The address error (level
12), stack error (level 13) and oscillator error (level 14)
traps fall into this category.
Each hard trap that occurs must be acknowledged
before code execution of any type may continue. If a
lower priority hard trap occurs while a higher priority
trap is pending, acknowledged, or is being processed,
a hard trap conflict will occur.
The device is automatically Reset in a hard trap conflict
condition. The TRAPR Status bit (RCON<15>) is set
when the Reset occurs, so that the condition may be
detected in software.
FIGURE 4-1:
TRAP VECTORS
IVT
AIVT
Reset - GOTO Instruction
Reset - GOTO Address
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved Vector
Reserved Vector
Reserved Vector
Interrupt 0 Vector
Interrupt 1 Vector
—
—
—
Interrupt 52 Vector
Interrupt 53 Vector
Reserved
Reserved
Reserved
Oscillator Fail Trap Vector
Stack Error Trap Vector
Address Error Trap Vector
Math Error Trap Vector
Reserved Vector
Reserved Vector
Reserved Vector
Interrupt 0 Vector
Interrupt 1 Vector
—
—
—
Interrupt 52 Vector
Interrupt 53 Vector
0x000000
0x000002
0x000004
0x000014
0x00007E
0x000080
0x000082
0x000084
0x000094
0x0000FE
DS70116J-page 38
© 2011 Microchip Technology Inc.