DSPIC30F5013-20I Datasheet, PDF (133/220 Pages) Microchip Technology – 16-bit Digital Signal Controllers

19.9 Module Power-down Modes
The module has two internal Power modes.
When the ADON bit is ‘1’, the module is in Active mode,
and is fully powered and functional.
When ADON is ‘0’, the module is in Off mode. The dig-
ital and analog portions of the circuit are disabled for
maximum current savings.
In order to return to the Active mode from Off mode, the
user must wait for the ADC circuitry to stabilize.
19.10 ADC Operation During CPU Sleep
and Idle Modes
19.10.1 ADC OPERATION DURING CPU
SLEEP MODE
When the device enters Sleep mode, all clock sources
to the module are shutdown and stay at logic ‘0’.
If Sleep occurs in the middle of a conversion, the con-
version is aborted. The converter will not continue with
a partially completed conversion on exit from Sleep
mode.
Register contents are not affected by the device
entering or leaving Sleep mode.
The ADC module can operate during Sleep mode if the
ADC clock source is set to RC (ADRC = 1). When the
RC clock source is selected, the ADC module waits one
instruction cycle before starting the conversion. This
allows the SLEEP instruction to be executed, which
eliminates all digital switching noise from the conver-
sion. When the conversion is complete, the DONE bit is
cleared and the result is loaded into the ADCBUF
register.
If the ADC interrupt is enabled, the device wakes up
from Sleep. If the ADC interrupt is not enabled, the
ADC module is turned off, although the ADON bit
remains set.
dsPIC30F5011/5013
19.10.2 A/D OPERATION DURING CPU IDLE
MODE
The ADSIDL bit selects if the module stops on Idle or
continues on Idle. If ADSIDL = 0, the module continues
operation on assertion of Idle mode. If ADSIDL = 1, the
module stops on Idle.
19.11 Effects of a Reset
A device Reset forces all registers to their Reset state.
This forces the ADC module to be turned off, and any
conversion and sampling sequence to be aborted. The
values that are in the ADCBUF registers are not modi-
fied. The ADC Result register contains unknown data
after a Power-on Reset.
19.12 Output Formats
The ADC result is 12 bits wide. The data buffer RAM is
also 12 bits wide. The 12-bit data can be read in one of
four different formats. The FORM<1:0> bits select the
format. Each of the output formats translates to a 16-bit
result on the data bus.
© 2011 Microchip Technology Inc.
DS70116J-page 133