DSPIC33FJ64GS606-IPT Datasheet, PDF (37/456 Pages) Microchip Technology – 16-Bit Digital Signal Controllers with High-Speed PWM, ADC and Comparators

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED)
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
IPL<2:0>: CPU Interrupt Priority Level Status bits^(2,3)
111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progress
N: MCU ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of a magnitude that
causes the sign bit to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
Z: MCU ALU Zero bit
1 = An operation that affects the Z bit has set it at some time in the past
0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)
C: MCU ALU Carry/Borrow bit
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
2:
3:
4:
This bit can be read or cleared (not set).
The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level (IPL). The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>).
Clearing this bit will clear SA and SB.
 2009-2012 Microchip Technology Inc.
DS70591E-page 37