MIC45116 Datasheet, PDF (27/42 Pages) Microchip Technology – 20V/6A DC/DC Power Module

6.0 PCB LAYOUT GUIDELINES
PCB layout is critical to achieve reliable, stable and
efficient performance. A ground plane is required to
control EMI and minimize the inductance in power,
signal and return paths. The following guidelines
should be followed to ensure proper operation of the
MIC45116 module.
6.1 Module
• Place the module close to the point-of-load.
• Use wide polygons to route the input and output
power lines.
• Follow the instructions in Package Information
and Recommended Landing Pattern to connect
the Ground exposed pads to system ground
planes.
6.2 Input Capacitor
• Place the input capacitors on the same side of the
board and as close to the module as possible.
• Place several vias to the ground plane close to
the input capacitor ground terminal.
• Use either X7R or X5R dielectric input capacitors.
Do not use Y5V or Z5U type capacitors.
• Do not replace the ceramic input capacitor with
any other type of capacitor. Any type of capacitor
can be placed in parallel with the ceramic input
capacitor.
• If a non-ceramic input capacitor is placed in
parallel with the input capacitor, it must be
recommended for switching regulator applications
and the operating voltage.
• In “Hot-Plug” applications, an electrolytic bypass
capacitor must be used to limit the over-voltage
spike seen on the input supply with power is
suddenly applied. If hot-plugging is the normal
operation of the system, using an appropriate
hot-swap IC is recommended.
6.3 RC Snubber (Optional)
• Depending on the operating conditions, a RC
snubber can be used. Place the RC and as close
to the SW pin as possible if needed. Placement of
the snubber on the same side as module is
preferred.
6.4 SW Node
• Do not route any digital lines underneath or close
to the SW node.
• Keep the switch node (SW) away from the
feedback (FB) pin.
MIC45116
6.5 Output Capacitor
• Use a wide trace to connect the output capacitor
ground terminal to the input capacitor ground
terminal.
• Phase margin will change as the output capacitor
value and ESR changes.
• The feedback trace should be separate from the
power trace and connected as close as possible
to the output capacitor. Sensing a long
high-current load trace can degrade the DC load
regulation.
Figure 6-1 is optimized from a small form factor point of
view shows top and bottom layer of a four layer PCB. It
is recommended to use mid layer 1 as a continuous
ground plane.
FIGURE 6-1:
Top and Bottom of a
Four-Layer Board.
 2016 Microchip Technology Inc.
DS20005571A-page 27