MIC45116 Datasheet, PDF (18/42 Pages) Microchip Technology – 20V/6A DC/DC Power Module

MIC45116
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
Pin Number Pin Name
Description
1, 2, 52
4, 44
5, 6
8-10, 48-51
12-21
23-25, 27-30,
32-34, 40, 41
26, 31, 35, 42,
45
36
37
38
39
43
47
3, 7, 11, 22, 46
—
—
—
PV_IN
PV_DD
BST
SW
V_OUT
NC
Power Input Voltage. Connection to the drain of the internal high-side power
MOSFET. Connect an input capacitor from PV_IN to P_GND.
Supply input for the internal power MOSFET drivers. Connect PV_DD pins together. Do
not leave floating.
Connection to the internal bootstrap circuitry and high-side power MOSFET drive
circuitry. Connect the two BST pins together.
The SW pin connects directly to the switch node. Due to the high-speed switching on
this pin, the SW pin should be routed away from sensitive nodes. The SW pin also
senses the current by monitoring the voltage across the low-side MOSFET during
OFF time.
Output Voltage. Connected to the internal inductor, the output capacitor should be
connected from this pin to P_GND as close to the module as possible.
Not internally connected.
P_GND
Power Ground. P_GND is the return path for the step-down power module power stage.
The P_GND pin connects to the source of internal low-side power MOSFET, the
negative terminals of input capacitors, and the negative terminals of output capacitors.
Signal Ground and Power Ground of MIC45116 are internally connected.
FB
Feedback. Input to the transconductance amplifier of the control loop. The FB pin is
referenced to 0.8V. A resistor divider connecting the feedback to the output is used to
set the desired output voltage. Connect the bottom resistor from FB to system ground.
External ripple injection (series R and C) can be connected between FB and SW.
PG Power Good. Open-Drain Output. If used, connect to an external pull-up resistor of at
least 10 kΩ between PG and the external bias voltage.
EN Enable. A logic signal to enable or disable the step-down regulator module operation.
The EN pin is TTL/CMOS compatible. Logic-high = enable, logic-low = disable or
shutdown. EN pin has an internal 1 MΩ (typical) pull-down resistor to GND. Do not
leave floating.
V_IN
5V_DD
Input for the internal linear regulator. Allows for split supplies to be used when there is
an external bus voltage available. Connect to PV_IN for single supply operation.
Bypass with a 0.1 µF capacitor from V_IN to P_GND.
Internal +5V Linear Regulator Output. Powered by V_IN, 5V_DD is the internal supply
bus for the device. In the applications with V_IN < +5.5V, 5V_DD should be tied to V_IN to
bypass the linear regulator.
I_LIM
Current Limit. Connect a resistor between I_LIM and SW to program the current limit.
KEEPOUT Depopulated pin positions.
V_OUT ePad V_OUT Exposed Pad. Internally connected to V_OUT pins. Please see the PCB Layout
Guidelines section.
SW ePad SW Exposed Pad. Internally connected to SW pins. Please see the PCB Layout
Guidelines section.
P_GND
ePAD
P_GND Exposed Pads. Please see the PCB Layout Guidelines section for the
connection to the system Ground.
DS20005571A-page 18
 2016 Microchip Technology Inc.