DSPIC33FJ06GS001_12 Datasheet, PDF (257/352 Pages) Microchip Technology – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, ADC and Comparators

dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
22.4 Watchdog Timer (WDT)
The Watchdog Timer (WDT) is driven by the LPRC
oscillator. When the WDT is enabled, the clock source is
also enabled.
22.4.1 PRESCALER/POSTSCALER
The nominal WDT clock source from LPRC is 32 kHz.
This feeds a prescaler that can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the WDTPRE Configuration bit
(FWDT<4>). With a 32 kHz input, the prescaler yields
a nominal WDT time-out period (TWDT) of 1 ms in 5-bit
mode or 4 ms in 7-bit mode.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPOST<3:0>
Configuration bits (FWDT<3:0>), which allow the
selection of 16 settings, from 1:1 to 1:32,768. Using the
prescaler and postscaler, time-out periods ranging from
1 ms to 131 seconds can be achieved.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSC<2:0> bits) or by
hardware (i.e., Fail-Safe Clock Monitor)
• When a PWRSAV instruction is executed
(i.e., Sleep or Idle mode is entered)
• When the device exits Sleep or Idle mode to
resume normal operation
• By a CLRWDT instruction during normal execution
Note:
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
22.4.2 SLEEP AND IDLE MODES
If the WDT is enabled, it will continue to run during
Sleep or Idle modes. When the WDT time-out occurs,
the device will wake the device and code execution will
continue from where the PWRSAV instruction was
executed. The corresponding SLEEP bit (RCON<3>)
or IDLE bit (RCON<2>) will need to be cleared in
software after the device wakes up.
22.4.3 ENABLING WDT
The WDT is enabled or disabled by the FWDTEN
Configuration bit in the FWDT Configuration register
(FWDT<7>). When the FWDTEN Configuration bit is
set, the WDT is always enabled.
The WDT can be optionally controlled in software when
the FWDTEN Configuration bit has been programmed
to ‘0’. The WDT is enabled in software by setting the
SWDTEN control bit (RCON<5>). The SWDTEN
control bit is cleared on any device Reset. The software
WDT option allows the user application to enable the
WDT for critical code segments and disable the WDT
during non-critical segments for maximum power
savings.
The WDT flag bit, WDTO (RCON<4>), is not automatically
cleared following a WDT time-out. To detect subsequent
WDT events, the flag must be cleared in software.
FIGURE 22-2:
WDT BLOCK DIAGRAM
All Device Resets
Transition to New Clock Source
Exit Sleep or Idle Mode
PWRSAV Instruction
CLRWDT Instruction
SWDTEN
FWDTEN
LPRC Clock
WDTPRE
Prescaler ^RS
(Divide-by-N1)
Watchdog Timer
WDTPOST<3:0>
RS _Postscaler
(Divide-by-N2)
Sleep/Idle
1
0
WDT
Wake-up
WDT
Reset
WDT Window Select
CLRWDT Instruction
 2011-2012 Microchip Technology Inc.
DS75018C-page 257