DSPIC33FJ06GS001_12 Datasheet, PDF (128/352 Pages) Microchip Technology – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, ADC and Comparators

dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 8-2: CLKDIV: CLOCK DIVISOR REGISTER⁽²⁾
R/W-0
ROI
R/W-0
R/W-1
DOZE<2:0>
R/W-1
R/W-0
DOZEN⁽¹⁾
bit 15
R/W-0
R/W-0
FRCDIV<2:0>
R/W-0
bit 8
R/W-0
R/W-1
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PLLPOST<1:0>
—
PLLPRE<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14-12
bit 11
bit 10-8
bit 7-6
bit 5
bit 4-0
ROI: Recover on Interrupt bit
1 = Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1
0 = Interrupts have no effect on the DOZEN bit
DOZE<2:0>: Processor Clock Reduction Select bits
111 = FCY/128
110 = FCY/64
101 = FCY/32
100 = FCY/16
011 = FCY/8 (default)
010 = FCY/4
001 = FCY/2
000 = FCY/1
DOZEN: Doze Mode Enable bit⁽¹⁾
1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks
0 = Processor clock/peripheral clock ratio is forced to 1:1
FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits
111 = FRC divide-by-256
110 = FRC divide-by-64
101 = FRC divide-by-32
100 = FRC divide-by-16
011 = FRC divide-by-8
010 = FRC divide-by-4
001 = FRC divide-by-2
000 = FRC divide-by-1 (default)
PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler)
11 = Output/8
10 = Reserved
01 = Output/4 (default)
00 = Output/2
Unimplemented: Read as ‘0’
PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler)
11111 = Input/33
•
•
•
00001 = Input/3
00000 = Input/2 (default)
Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs.
2: This register is reset only on a Power-on Reset (POR).
DS75018C-page 128
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