DSPIC33FJ16GS504T-E Datasheet, PDF (256/346 Pages) Microchip Technology – High-Performance, 16-bit Digital Signal Controllers

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
REGISTER 19-7: ADCPC2: A/D CONVERT PAIR CONTROL REGISTER 2⁽¹⁾
R/W-0
IRQEN5
bit 15
R/W-0
PEND5
R/W-0
SWTRG5
R/W-0
R/W-0
R/W-0
R/W-0
TRGSRC5<4:0>
R/W-0
bit 8
R/W-0
IRQEN4
bit 7
R/W-0
PEND4
R/W-0
SWTRG4
R/W-0
R/W-0
R/W-0
R/W-0
TRGSRC4<4:0>
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
IRQEN5: Interrupt Request Enable 5 bit
1 = Enable IRQ generation when requested conversion of channels AN11 and AN10 is completed
0 = IRQ is not generated
PEND5: Pending Conversion Status 5 bit
1 = Conversion of channels AN11 and AN10 is pending; set when selected trigger is asserted
0 = Conversion is complete
SWTRG5: Software Trigger 5 bit
1 = Start conversion of AN11 and AN10 (if selected in TRGSRC bits)⁽²⁾
This bit is automatically cleared by hardware when the PEND5 bit is set.
0 = Conversion is not started
Note 1: This register is only implemented on the dsPIC33FJ16GS504 devices.
2: If other conversions are in progress, then conversion will be performed when the conversion resources are
available.
DS70318D-page 254
Preliminary
© 2009 Microchip Technology Inc.