TC1307 Datasheet, PDF (19/28 Pages) Microchip Technology – Four-Channel CMOS LDO with Select Mode, Shutdown and Independent Reset

5.6.2 OVER TEMPERATURE PROTECTION
If the internal power dissipation within the TC1307 is
excessive due to a faulted load or higher than specified
line voltage, an internal temperature sensing element
will prevent the junction temperature from exceeding
approximately 150°C. If the junction temperature does
exceed approximately 150°C, all LDO outputs will be
disabled until the junction temperature cools to approx-
imately 140°C, at which point the device will resume
normal operation. The RESET output will continue to
operate normally in the event of a thermal shutdown.
5.7 Recommended Physical Layout
Figure 5-2 represents a typical layout using the
TC1307 16-pin QSOP package. C₁, C₂, C₃ and C₄ are
1 µF X5R 0603 ceramic output capacitors and C_IN is a
2.2 µF X5R 0805 ceramic capacitor. No other compo-
nents are required for this quad output LDO with micro-
controller reset function. Utilizing the highly integrated
TC1307, the total board area required is less than
0.300 square inches.
For CMOS LDOs, the GND or quiescent current is
small when compared to the maximum output current
capability. The GND pins connected to the TC1307 do
not carry high current and it is not necessary for them
TC1307
to be wide. It is more important for the GND pins to be
connected to a quiet circuit ground. Noise on the GND
pins may result in noise at the output of the LDO. In
Figure 5-2, a ground plane is used to connect the
TC1307 Pins to the GND plane that has the V_OUT
capacitor return tied to it. For applications that have rip-
ple voltage on the input, the C_IN capacitor return can be
separated from the ground plane by running a trace
from the capacitor to the ground plane. This impedance
will help to reduce the noise on the output of the LDO.
The output voltage regulation uses the GND pins of the
TC1307 as the return path for the internal bandgap ref-
erence. Any voltage drops between the load and the
respective V_OUT pin and GND pin will show up as regu-
lation losses. It is important to size the V_OUT and GND
conductors for minimum voltage drops. The maximum
application load current will determine how large these
traces should be. As shown in Figure 5-2, a ground
plane can be used minimize the trace resistance from
the load to the TC1307 GND pin.
SHDN1
Pin 1
CIN
SHDN3
Backplane Traces
FIGURE 5-2: TC1307 Typical Layout.
SHDN2
C1 _C2
RESET
VOUT1
VOUT2
VOUT3
C4 ^C3
VOUT4
SHDN4
= GND Plane
= Top Metal Layer
 2002 Microchip Technology Inc.
DS21702A-page 19