TC1307 Datasheet, PDF (18/28 Pages) Microchip Technology – Four-Channel CMOS LDO with Select Mode, Shutdown and Independent Reset

TC1307
P_D(MAX) = ⁽---^T---^J---⁽--^M----^A---^X---⁾-_θ--–-_J---_A-^T---^A----⁽--^M----^A---^X---⁾--⁾-
5.5 Typical Application
Internal power dissipation, junction temperature rise,
junction temperature and maximum power dissipation
are calculated in the following example. The power dis-
sipation as a result of quiescent current and RESET
output are small enough to be neglected.
Input Voltage:
V_IN = 3.1V to 4.1V
LDO Output Voltages and Currents:
V_OUT1 = 3.0V
I_IOUT1 = 100 mA
V_OUT2 = 3.0V
I_IOUT2 = 100 mA
V_OUT3 = 1.8V
I_IOUT3 = 60 mA
V_OUT4 = 1.8V
I_IOUT4 = 60 mA
Maximum Ambient Temperature:
T_A(MAX)= 50°C
Internal Power Dissipation:
Internal Power dissipation is the sum of the power dis-
sipation for each LDO pass device.
P_LDO1 = (V_IN(MAX)-V_OUT1(MIN)) x I_OUT1(MAX)
P_LDO1 = (4.1V - (0.975 x 3.0V)) x 100 mA
P_LDO1 = 117.5 milli-Watts
P_LDO2 = (4.1V - (0.975 x 3.0V)) x 100 mA
P_LDO2 = 117.5 milli-Watts
P_LDO3 = (4.1V - (0.975 x 1.8V)) x 60 mA
P_LDO3 = (2.35V x 60 mA)
P_LDO3 = 140.7 milli-Watts
P_LDO4 = (4.1V - (0.975 x 1.8V)) x 60 mA
P_LDO4 = 140.7 milli-Watts
P_TOTAL = P_LDO1 + P_LDO2 + P_LDO3 + P_LDO4
P_TOTAL = 516.4 milli-Watts
Device Junction Temperature Rise
The internal junction temperature rise is a function of
internal power dissipation and the thermal resistance
from junction to ambient for the application. The ther-
mal resistance from junction to air (θ_JA) is derived from
an EIA/JEDEC standard for measuring thermal resis-
tance for small surface mount packages. The EIA/
JEDEC specification is JESD51-7 “High Effective Ther-
mal Conductivity Test Board for Leaded Surface Mount
Packages”. The standard describes the test method
and board specifications for measuring the thermal
resistance from junction to case. The actual thermal
resistance for a particular application can vary depend-
ing on many factors such as copper area and thick-
ness. Refer to AN792 for more information regarding
this subject.
T_JRISE = P_TOTAL x θ_JA
T_JRISE = 516.4 milli-Watts x 112.4°C/Watt
T_JRISE = 58.1°C
Junction Temperature Estimate
To estimate the internal junction temperature (T_J), the
calculated junction temperature rise (T_JRISE) is added
to the ambient or offset temperature (T_AMBIENT). For
this example the worst case junction temperature is
estimated below.
T_J =T_JRISE + T_AMBIENT
T_J =108.1°C
Maximum Package Power Dissipation
The maximum power dissipation capability for the
TC1307 can be approximated by finding the maximum
allowable temperature rise from junction to case and
dividing that by the estimated thermal resistance of the
application. For this example, the maximum allowable
junction temperature rise is 125°C - 50°C or 75°C. By
dividing 75°C by the estimated thermal resistance
(112.4°C/Watt), the maximum allowable power dissipa-
tion is calculated to be 667.3 milli-Watts.
5.6 Device Protection
5.6.1 OVER CURRENT LIMIT
In the event of a faulted output load, the maximum cur-
rent the LDO will permit to flow is limited internally. For
each of the four LDO’s internal to the TC1307, the limit
in the event of a short circuit will be 360 mA typical.
This limit can be used to prevent damage to the circuit
board or connectors. The over current protection for
each LDO output is independent. For example, if LDO1
output is shorted to ground, the over current protection
will limit the output current for LDO1. If the junction tem-
perature does not rise above the typical 150°C thermal
shutdown point the other three LDO outputs (LDO2,
LDO3, LDO4) will remain within regulation.
DS21702A-page 18
 2002 Microchip Technology Inc.