MCP19111 Datasheet, PDF (166/222 Pages) Microchip Technology – Digitally Enhanced Power Analog Controller with Integrated Synchronous Driver

MCP19111
27.4.9 GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I²C bus is such that
the first byte after the Start condition usually
determines which device will be the slave addressed by
the master device. The exception is the general call
address, which can address all devices. When this
address is used, all devices should, in theory, respond
with an acknowledge.
The general call address is a reserved address in the
I²C protocol, defined as address 0x00. When the
GCEN bit of the SSPCON2 register is set, the slave
module will automatically ACK the reception of this
address, regardless of the value stored in SSPADDx.
After the slave clocks in an address of all zeros with the
R/W bit clear, an interrupt is generated and slave
software can read SSPBUF and respond. Figure 27-16
shows a general call reception sequence.
In 10-bit Address mode, the UA bit will not be set on the
reception of the general call address. The slave will
prepare to receive the second byte as data, just as it
would in the 7-bit mode.
If the AHEN bit of the SSPCON3 register is set, just as
with any other address reception, the slave hardware
will stretch the clock after the 8^th falling edge of SCL.
The slave must then set its ACKDT value and release
the clock with communication progressing as it would
normally.
FIGURE 27-16: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
SDA
General Call Address
Address is compared to General Call Address
after ACK, set interrupt
R/W = 0
Receiving Data
ACK
ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL
SSPIF
S
1 2 34 56 7891 2 34 5 6 789
BF (SSPSTAT<0>)
GCEN (SSPCON2<7>)
Cleared by software
SSPBUF is read
’1’
27.4.10 SSPMSKX REGISTER
An SSP Mask (SSPMSKx) register (Register 27-6 and
Register 27-8) is available in I²C Slave mode as a
mask for the value held in the SSPSRx register during
an address comparison operation. A zero (‘0’) bit in the
SSPMSKx register has the effect of making the
corresponding bit of the received address a “don’t
care”.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSP operation until written with a mask value.
The SSP Mask register is active during:
• 7-bit Address mode: address compare of A<7:1>.
• 10-bit Address mode: address compare of A<7:0>
only. The SSP mask has no effect during the
reception of the first (high) byte of the address.
DS22331A-page 166
 2013 Microchip Technology Inc.