DSPIC30F4011_10 Datasheet, PDF (160/238 Pages) Microchip Technology – High-Performance, 16-Bit Digital Signal Controllers

dsPIC30F4011/4012
Table 21-5 lists the Reset conditions for the RCON
Register. Since the control bits within the RCON regis-
ter are R/W, the information in the table implies that all
the bits are negated prior to the action specified in the
condition column.
TABLE 21-5: INITIALIZATION CONDITION FOR RCON REGISTER, CASE 1
Condition
Program
Counter
TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR
Power-on Reset
Brown-out Reset
0x000000 0
0x000000 0
0
0
0
0
0
0
11
0
0
0
0
0
0
01
MCLR Reset during normal 0x000000 0
operation
Software Reset during
normal operation
0x000000 0
MCLR Reset during Sleep 0x000000 0
0
1
0
0
0
0
00
0
0
1
0
0
0
00
0
1
0
0
0
1
00
MCLR Reset during Idle
0x000000 0
0
1
0
0
1
0
00
WDT Time-out Reset
0x000000 0
0
0
0
1
0
0
00
WDT Wake-up
Interrupt Wake-up from
Sleep
PC + 2
0
PC + 2⁽¹⁾
0
0
0
0
1
0
1
00
0
0
0
0
0
1
00
Clock Failure Trap
0x000004 0
0
0
0
0
0
0
00
Trap Reset
0x000000 1
0
0
0
0
0
0
00
Illegal Operation Trap
0x000000 0
1
0
0
0
0
0
00
Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
Table 21-6 lists a second example of the bit
conditions for the RCON register. In this case, it is not
assumed that the user has set/cleared specific bits
prior to action specified in the condition column.
TABLE 21-6: INITIALIZATION CONDITION FOR RCON REGISTER, CASE 2
Condition
Program
Counter
TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR
Power-on Reset
Brown-out Reset
0x000000 0
0x000000 u
0
0
0
0
0
0
11
u
u
u
u
u
u
01
MCLR Reset during normal 0x000000 u
operation
Software Reset during
normal operation
0x000000 u
MCLR Reset during Sleep 0x000000 u
u
1
0
0
0
0
uu
u
0
1
0
0
0
uu
u
1
u
0
0
1
uu
MCLR Reset during Idle
0x000000 u
u
1
u
0
1
0
uu
WDT Time-out Reset
0x000000 u
u
0
0
1
0
0
uu
WDT Wake-up
Interrupt Wake-up from
Sleep
PC + 2
u
PC + 2⁽¹⁾
u
u
u
u
1
u
1
uu
u
u
u
u
u
1
uu
Clock Failure Trap
0x000004 u
u
u
u
u
u
u
uu
Trap Reset
0x000000 1
u
u
u
u
u
u
uu
Illegal Operation Reset
0x000000 u
1
u
u
u
u
u
uu
Legend: u = unchanged
Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
DS70135G-page 160
© 2010 Microchip Technology Inc.