DSPIC30F4011_10 Datasheet, PDF (141/238 Pages) Microchip Technology – High-Performance, 16-Bit Digital Signal Controllers

20.1 A/D Result Buffer
The module contains a 16-word, dual port, read-only buf-
fer, called ADCBUF0...ADCBUFF, to buffer the A/D
results. The RAM is 10 bits wide, but is read into different
format 16-bit words. The contents of the sixteen A/D
Conversion Result Buffer registers, ADCBUF0 through
ADCBUFF, cannot be written by user software.
20.2 Conversion Operation
After the ADC module has been configured, the sample
acquisition is started by setting the SAMP bit. Various
sources, such as a programmable bit, timer time-outs
and external events, terminate acquisition and start a
conversion. When the A/D conversion is complete, the
result is loaded into ADCBUF0...ADCBUFF, and the A/D
Interrupt Flag, ADIF, and the DONE bit are set after the
number of samples specified by the SMPI<3:0> bits.
The following steps should be followed for doing an
A/D conversion:
1. Configure the ADC module:
- Configure analog pins, voltage reference
and digital I/O
- Select A/D input channels
- Select A/D conversion clock
- Select A/D conversion trigger
- Turn on ADC module
2. Configure the A/D interrupt (if required):
- Clear ADIF bit
- Select A/D interrupt priority
3. Start sampling.
4. Wait the required acquisition time.
5. Trigger acquisition end, start conversion.
6. Wait for A/D conversion to complete by either:
- Waiting for the A/D interrupt
- Waiting for the DONE bit to get set
7. Read A/D result buffer, clear ADIF if required.
20.3 Selecting the Conversion
Sequence
Several groups of control bits select the sequence in
which the A/D connects inputs to the sample/hold
channels, converts channels, writes the buffer memory
and generates interrupts. The sequence is controlled
by the sampling clocks.
The SIMSAM bit controls the acquire/convert
sequence for multiple channels. If the SIMSAM bit is
‘0’, the two or four selected channels are acquired and
converted sequentially with two or four sample clocks.
If the SIMSAM bit is ‘1’, two or four selected channels
are acquired simultaneously with one sample clock.
The channels are then converted sequentially.
Obviously, if there is only 1 channel selected, the
SIMSAM bit is not applicable.
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
The CHPS<1:0> bits select how many channels are
sampled. This selection can vary from 1, 2 or 4 channels.
If the CHPS bits select 1 channel, the CH0 channel is
sampled at the sample clock and converted. The result is
stored in the buffer. If the CHPS bits select 2 channels,
the CH0 and CH1 channels are sampled and converted.
If the CHPS bits select 4 channels, the CH0, CH1, CH2
and CH3 channels are sampled and converted.
The SMPI<3:0> bits select the number of acquisition/
conversion sequences that would be performed before
an interrupt occurs. This can vary from 1 sample per
interrupt to 16 samples per interrupt.
The user cannot program a combination of CHPS and
SMPI bits that specifies more than 16 conversions per
interrupt, or 8 conversions per interrupt, depending
on the BUFM bit. The BUFM bit, when set, splits the
16-word results buffer (ADCBUF0 to ADCBUFF) into
two, 8-word groups. Writing to the 8-word buffers is
alternated on each interrupt event. Use of the BUFM bit
depends on how much time is available for moving data
out of the buffers after the interrupt, as determined by
the application.
If the processor can quickly unload a full buffer within
the time it takes to acquire and convert one channel,
the BUFM bit can be ‘0’ and up to 16 conversions
may be done per interrupt. The processor has one
sample-and-conversion time to move the sixteen
conversions.
If the processor cannot unload the buffer within the
acquisition and conversion time, the BUFM bit should be
‘1’. For example, if SMPI<3:0> (ADCON2<5:2>) = 0111,
then eight conversions are loaded into half of the buffer,
following which an interrupt occurs. The next eight
conversions are loaded into the other half of the buffer.
The processor has the entire time between interrupts to
move the eight conversions.
The ALTS bit can be used to alternate the inputs
selected during the sampling sequence. The input
multiplexer has two sets of sample inputs: MUX A and
MUX B. If the ALTS bit is ‘0’, only the MUX A inputs are
selected for sampling. If the ALTS bit is ‘1’ and
SMPI<3:0> = 0000, on the first sample/convert
sequence, the MUX A inputs are selected, and on the
next acquire/convert sequence, the MUX B inputs are
selected.
The CSCNA bit (ADCON2<10>) allows the CH0
channel inputs to be alternately scanned across a
selected number of analog inputs for the MUX A group.
The inputs are selected by the ADCSSL register. If a
particular bit in the ADCSSL register is ‘1’, the corre-
sponding input is selected. The inputs are always
scanned from lower to higher numbered inputs, starting
after each interrupt. If the number of inputs selected is
greater than the number of samples taken per interrupt,
the higher numbered inputs are unused.
DS70135G-page 141