DSPIC30F4011_10 Datasheet, PDF (12/238 Pages) Microchip Technology – High-Performance, 16-Bit Digital Signal Controllers

dsPIC30F4011/4012
Table 1-1 provides a brief description of the device I/O
pinout and the functions that are multiplexed to a port
pin. Multiple functions may exist on one port pin. When
multiplexing occurs, the peripheral module’s functional
requirements may force an override of the data
direction of the port pin.
TABLE 1-1: dsPIC30F4011 I/O PIN DESCRIPTIONS
Pin Name
Pin
Type
Buffer
Type
Description
AN0-AN8
I
Analog Analog input channels. AN0 and AN1 are also used for device programming
data and clock inputs, respectively.
AVDD
P
P
Positive supply for analog module. This pin must be connected at all times.
AVSS
P
P
Ground reference for analog module. This pin must be connected at all times.
CLKI
CLKO
I ST/CMOS External clock source input. Always associated with OSC1 pin function.
O
— Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
CN0-CN7
I
CN17-CN18
ST Input change notification inputs. Can be software programmed for internal
weak pull-ups on all inputs.
C1RX
C1TX
I
ST CAN1 bus receive pin.
O
— CAN1 bus transmit pin.
EMUD
EMUC
EMUD1
EMUC1
EMUD2
EMUC2
EMUD3
EMUC3
I/O
ST ICD Primary Communication Channel data input/output pin.
I/O
ST ICD Primary Communication Channel clock input/output pin.
I/O
ST ICD Secondary Communication Channel data input/output pin.
I/O
ST ICD Secondary Communication Channel clock input/output pin.
I/O
ST ICD Tertiary Communication Channel data input/output pin.
I/O
ST ICD Tertiary Communication Channel clock input/output pin.
I/O
ST ICD Quaternary Communication Channel data input/output pin.
I/O
ST ICD Quaternary Communication Channel clock input/output pin.
IC1, IC2, IC7,
I
IC8
ST Capture inputs 1, 2, 7 and 8.
INDX
QEA
QEB
I
ST Quadrature Encoder Index Pulse input.
I
ST Quadrature Encoder Phase A input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
I
ST Quadrature Encoder Phase B input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
INT0
INT1
INT2
I
ST External interrupt 0.
I
ST External interrupt 1.
I
ST External interrupt 2.
FLTA
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
I
ST PWM Fault A input.
O
— PWM1 low output.
O
— PWM1 high output.
O
— PWM2 low output.
O
— PWM2 high output.
O
— PWM3 low output.
O
— PWM3 high output.
MCLR
I/P
ST Master Clear (Reset) input or programming voltage input. This pin is an
active-low Reset to the device.
OCFA
I
ST Compare Fault A input (for Compare channels 1, 2, 3 and 4).
OC1-OC4
O
— Compare outputs 1 through 4.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I
= Input
Analog = Analog input
O
= Output
P
= Power
DS70135G-page 12
© 2010 Microchip Technology Inc.