DSPIC33FJ64GP204-I Datasheet, PDF (16/436 Pages) Microchip Technology – 16-bit Digital Signal Controllers (up to 128 KB Flash and 16K SRAM) with Advanced Analog

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Type
Buffer
Type
PPS
Description
SCL1
SDA1
ASCL1
ASDA1
I/O
ST
No Synchronous serial clock input/output for I2C1.
I/O
ST
No Synchronous serial data input/output for I2C1.
I/O
ST
No Alternate synchronous serial clock input/output for I2C1.
I/O
ST
No Alternate synchronous serial data input/output for I2C1.
TMS
TCK
TDI
TDO
C1RX
C1TX
I
ST
No JTAG Test mode select pin.
I
ST
No JTAG test clock input pin.
I
ST
No JTAG test data input pin.
O
—
No JTAG test data output pin.
I
ST
Yes ECAN1 bus receive pin.
O
—
Yes ECAN1 bus transmit pin.
RTCC
O
—
No Real-Time Clock Alarm Output.
CVREF
O
ANA
No Comparator Voltage Reference Output.
C1IN-
C1IN+
C1OUT
I
ANA
No Comparator 1 Negative Input.
I
ANA
No Comparator 1 Positive Input.
O
—
Yes Comparator 1 Output.
C2IN-
C2IN+
C2OUT
I
ANA
No Comparator 2 Negative Input.
I
ANA
No Comparator 2 Positive Input.
O
—
Yes Comparator 2 Output.
PMA0
I/O
PMA1
I/O
PMA2 -PMPA10 O
PMBE
O
PMCS1
O
PMD0-PMPD7 I/O
PMRD
O
PMWR
O
TTL/ST
TTL/ST
—
—
—
TTL/ST
—
—
No Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and
Output (Master modes).
No Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and
Output (Master modes).
No Parallel Master Port Address (Demultiplexed Master Modes).
No Parallel Master Port Byte Enable Strobe.
No Parallel Master Port Chip Select 1 Strobe.
No Parallel Master Port Data (Demultiplexed Master mode) or Address/
Data (Multiplexed Master modes).
No Parallel Master Port Read Strobe.
No Parallel Master Port Write Strobe.
DAC1RN
DAC1RP
DAC1RM
O
—
No DAC1 Right Channel Negative Output.
O
—
No DAC1 Right Channel Positive Output.
O
—
No DAC1 Right Channel Middle Point Value (typically 1.65V).
DAC1LN
DAC1LP
DAC1LM
O
—
No DAC1 Left Channel Negative Output.
O
—
No DAC1 Left Channel Positive Output.
O
—
No DAC1 Left Channel Middle Point Value (typically 1.65V).
COFS
I/O
ST
Yes Data Converter Interface frame synchronization pin.
CSCK
CSDI
I/O
ST
Yes Data Converter Interface serial clock input/output pin.
I
ST
Yes Data Converter Interface serial data input pin
CSDO
O
—
Yes Data Converter Interface serial data output pin.
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O
ST
No Data I/O pin for programming/debugging communication channel 1.
I
ST
No Clock input pin for programming/debugging communication channel 1.
I/O
ST
No Data I/O pin for programming/debugging communication channel 2.
I
ST
No Clock input pin for programming/debugging communication channel 2.
I/O
ST
No Data I/O pin for programming/debugging communication channel 3.
I
ST
No Clock input pin for programming/debugging communication channel 3.
MCLR
I/P
ST
No Master Clear (Reset) input. This pin is an active-low Reset to the
device.
AVDD
P
P
No Positive supply for analog modules. This pin must be connected at all
times.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Analog = Analog input P = Power
O = Output
I = Input
PPS = Peripheral Pin Select
DS70292G-page 16
© 2007-2012 Microchip Technology Inc.