DSPIC30F5015_07 Datasheet, PDF (156/230 Pages) Microchip Technology – High-Performance, 16-Bit Digital Signal Controllers

dsPIC30F5015/5016
The configuration guidelines give the required setup
values for the conversion speeds above 500 ksps,
since they require external VREF pins usage and there
are some differences in the configuration procedure.
Configuration details that are not critical to the
conversion speed have been omitted.
The following figure depicts the recommended circuit
for the conversion rates above 500 ksps.
FIGURE 21-2:
ADC VOLTAGE REFERENCE SCHEMATIC
VDD
VDD
VDD
R2
10
C2
0.1 μF
R1
10
C1
0.01 μF
1
2
3
4
5
6
MCLR
8
VSS
VDD
11
12
13
14
VREF-
VREF+
dsPIC30F5015
AVDD
VDD
48
47
46
VDD
VDD
VDD
45
44
C8
1 mF
C7
C6
0.1 mF 0.01 mF
43
42
VSS
40
39
VDD
VDD
37
VDD
VDD
VDD
36
35
C5
C4
C3
34
1 mF 0.1 mF 0.01 mF
33
21.7.1 1 Msps CONFIGURATION
GUIDELINE
The configuration for 1 Msps operation is dependent on
whether a single input pin is to be sampled or whether
multiple pins will be sampled.
21.7.1.1 Single Analog Input
For conversions at 1 Msps for a single analog input, at
least two sample and hold channels must be enabled.
The analog input multiplexer must be configured so
that the same input pin is connected to both sample
and hold channels. The ADC converts the value held
on one S/H channel, while the second S/H channel
acquires a new input sample.
21.7.1.2 Multiple Analog Inputs
The ADC can also be used to sample multiple analog
inputs using multiple sample and hold channels. In this
case, the total 1 Msps conversion rate is divided among
the different input signals. For example, four inputs can
be sampled at a rate of 250 ksps for each signal or two
inputs could be sampled at a rate of 500 ksps for each
signal. Sequential sampling must be used in this con-
figuration to allow adequate sampling time on each
input.
DS70149C-page 154
© 2007 Microchip Technology Inc.