DSPIC30F5015_07 Datasheet, PDF (142/230 Pages) Microchip Technology – High-Performance, 16-Bit Digital Signal Controllers

dsPIC30F5015/5016
20.3.1 POR: POWER-ON RESET
A power-on event will generate an internal POR pulse
when a VDD rise is detected. The Reset pulse will occur
at the POR circuit threshold voltage (VPOR), which is
nominally 1.85V. The device supply voltage character-
istics must meet specified starting voltage and rise rate
requirements. The POR pulse will reset a POR timer
and place the device in the Reset state. The POR also
selects the device clock source identified by the
oscillator configuration fuses.
The POR circuit inserts a small delay, TPOR, which is
nominally 10 μs and ensures that the device bias
circuits are stable. Furthermore, a user selected power-
up time-out (TPWRT) is applied. The TPWRT parameter
is based on Configuration bits and can be 0 ms (no
delay), 4 ms, 16 ms or 64 ms. The total delay is at
device power-up TPOR + TPWRT. When these delays
have expired, SYSRST will be negated on the next
leading edge of the Q1 clock, and the PC will jump to
the Reset vector.
The timing for the SYSRST signal is shown in
Figure 20-3 through Figure 20-5.
FIGURE 20-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
Internal POR
OST Time-out
PWRT Time-out
TOST
TPWRT
Internal Reset
FIGURE 20-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
Internal POR
OST Time-out
PWRT Time-out
Internal Reset
TOST
TPWRT
DS70149C-page 140
© 2007 Microchip Technology Inc.