DSPIC30F5015_07 Datasheet, PDF (109/230 Pages) Microchip Technology – High-Performance, 16-Bit Digital Signal Controllers

17.0 I²C MODULE
Note: This data sheet summarizes features of this
group of dsPIC30F devices and is not intended to be
a complete reference source. For more information
on the CPU, peripherals, register descriptions and
general device functionality, refer to the “dsPIC30F
Family Reference Manual” (DS70046).
The Inter-Integrated Circuit (I²C) module provides
complete hardware support for both Slave and Multi-
Master modes of the I²C serial communication
standard, with a 16-bit interface.
This module offers the following key features:
• I²C interface supporting both Master and Slave
operation.
• I²C Slave mode supports 7 and 10-bit address.
• I²C Master mode supports 7 and 10-bit address.
• I²C port allows bidirectional transfers between
master and slaves.
• Serial clock synchronization for I²C port can be
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control).
• I²C supports Multi-Master operation; detects bus
collision and will arbitrate accordingly.
FIGURE 17-1:
PROGRAMMER’S MODEL
bit 7
bit 7
bit 8
bit 15
bit 15
bit 9
17.1.3 I²C REGISTERS
I2CCON and I2CSTAT are control and status registers,
respectively. The I2CCON register is readable and writ-
able. The lower 6 bits of I2CSTAT are read-only. The
remaining bits of the I2CSTAT are read/write.
I2CRSR is the Shift register used for shifting data,
whereas I2CRCV is the Buffer register to which data
bytes are written, or from which data bytes are read.
I2CRCV is the Receive buffer, as shown in Figure 16-1.
I2CTRN is the Transmit register to which bytes are writ-
ten during a transmit operation, as shown in Figure 16-2.
dsPIC30F5015/5016
17.1 Operating Function Description
The hardware fully implements all the master and slave
functions of the I²C Standard and Fast mode
specifications, as well as 7 and 10-bit addressing.
Thus, the I²C module can operate either as a slave or
a master on an I²C bus.
17.1.1 VARIOUS I²C MODES
The following types of I²C operation are supported:
• I²C Slave operation with 7-bit address
• I²C Slave operation with 10-bit address
• I²C Master operation with 7 or 10-bit address
See the I²C programmer’s model in Figure 17-1.
17.1.2 PIN CONFIGURATION IN I²C MODE
I²C has a 2-pin interface; pin SCL is clock and pin SDA
is data.
I2CRCV (8 bits)
bit 0
I2CTRN (8 bits)
bit 0
I2CBRG (9 bits)
bit 0
I2CCON (16 bits)
bit 0
I2CSTAT (16 bits)
bit 0
I2CADD (10 bits)
bit 0
The I2CADD register holds the slave address. A Status
bit, ADD10, indicates 10-bit Address mode. The
I2CBRG acts as the Baud Rate Generator (BRG)
reload value.
In receive operations, I2CRSR and I2CRCV together
form a double-buffered receiver. When I2CRSR receives
a complete byte, it is transferred to I2CRCV and an inter-
rupt pulse is generated. During transmission, the
I2CTRN is not double-buffered.
Note:
Following a Restart condition in 10-bit
mode, the user only needs to match the
first 7-bit address.
© 2007 Microchip Technology Inc.
DS70149C-page 107