MCP19124 Datasheet, PDF (154/236 Pages) Microchip Technology – Digitally-Enhanced Power Analog Synchronous Low-Side Dual-Loop PWM Controller

MCP19124/5
FIGURE 27-2:
PWMPHL
SIMPLIFIED PWM BLOCK DIAGRAM
PWMRL
8
PWMPHH
(SLAVE)
8
Comparator
8
PWMRH
(SLAVE)
8
Comparator
LATCH DATA
LATCH DATA
8
8
RQ
SQ
OSC SYSTEM
CLOCK
TMR2 ⁽¹⁾
(Note 1)
8
Comparator
RESET TIMER
WDM_ RESET
8
PR2
EN_ SS
CLKPIN_IN
Note 1: TIMER 2 should be clocked by F_OSC
A PWM output (Figure 27-3) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 27-3:
PWM OUTPUT
Period
Duty Cycle
TMR2 = PR2 + 1
TMR2 = PWMRH
TMR2 = PR2 + 1
27.1.3 PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following equation.
EQUATION 27-2:
PWMPERIOD = PR2 + 1  TOSC  T2PRESCALE _VALUE
When TMR2 is equal to PR2, the following two events
occur on the next increment cycle:
• TMR2 is cleared
• The PWM duty cycle is latched from PWMRL into
PWMRH
DS20005619A-page 154
 2016 Microchip Technology Inc.