MCP6041T-I Datasheet, PDF (14/40 Pages) Microchip Technology – 600 nA, Rail-to-Rail Input/Output Op Amps

MCP6041/2/3/4
4.5 MCP6043 Chip Select
The MCP6043 is a single op amp with Chip Select
(CS). When CS is pulled high, the supply current drops
to 50 nA (typical) and flows through the CS pin to V_SS.
When this happens, the amplifier output is put into a
high impedance state. By pulling CS low, the amplifier
is enabled. If the CS pin is left floating, the amplifier
may not operate properly. Figure 1-1 shows the output
voltage and supply current response to a CS pulse.
4.6 Supply Bypass
With this family of operational amplifiers, the power
supply pin (V_DD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high frequency performance. It can use a bulk
capacitor (i.e., 1 µF or larger) within 100 mm to provide
large, slow currents. This bulk capacitor is not required
for most applications and can be shared with nearby
analog parts.
4.7 Unused Op Amps
An unused op amp in a quad package (MCP6044)
should be configured as shown in Figure 4-5. These
circuits prevent the output from toggling and causing
crosstalk. Circuit A sets the op amp at its minimum
noise gain. The resistor divider produces any desired
reference voltage within the output voltage range of the
op amp; the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
current.
¼ MCP6044 (A)
V_DD
R₁
V_DD
R₂
V_REF
¼ MCP6044 (B)
V_DD
V_REF
=
V_DD

-------^R----²-------
R₁ + R₂
FIGURE 4-5:
Unused Op Amps.
4.8 PCB Surface Leakage
In applications where low input bias current is critical,
printed circuit board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 10¹²ï—. A 5V difference would
cause 5 pA of current to flow, which is greater than the
MCP6041/2/3/4 family’s bias current at +25°C (1 pA,
typical).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
Figure 4-6 shows an example of this type of layout.
Guard Ring V_IN– V_IN+
FIGURE 4-6:
Example Guard Ring Layout
for Inverting Gain.
1. Non-inverting Gain and Unity Gain Buffer:
a) Connect the non-inverting pin (V_IN+) to the
input with a wire that does not touch the
PCB surface.
b) Connect the guard ring to the inverting input
pin (V_IN–). This biases the guard ring to the
common mode input voltage.
2. Inverting Gain and Transimpedance Gain
(convert current to voltage, such as photo
detectors) amplifiers:
a) Connect the guard ring to the non-inverting
input pin (V_IN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., V_DD/2 or ground).
b) Connect the inverting pin (V_IN–) to the input
with a wire that does not touch the PCB
surface.
DS21669D-page 14
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