DSPIC33FJ64GP202-ESP Datasheet, PDF (129/436 Pages) Microchip Technology – 16-bit Digital Signal Controllers (up to 128 KB Flash and 16K SRAM) with Advanced Analog

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
8.0 DIRECT MEMORY ACCESS
(DMA)
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04,
and
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to Section 38. “Direct Memory
Access (DMA) (Part III)” (DS70215) of
the “dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
Direct Memory Access (DMA) is a very efficient
mechanism of copying data between peripheral SFRs
(e.g., UART Receive register, Input Capture 1 buffer),
and buffers or variables stored in RAM, with minimal
CPU intervention. The DMA controller can
automatically copy entire blocks of data without
requiring the user software to read or write the
peripheral Special Function Registers (SFRs) every
time a peripheral interrupt occurs. The DMA controller
uses a dedicated bus for data transfers and therefore,
does not steal cycles from the code execution flow of
the CPU. To exploit the DMA capability, the
corresponding user buffers or variables must be
located in DMA RAM.
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 peripherals that
can utilize DMA are listed in Table 8-1.
TABLE 8-1: DMA CHANNEL TO PERIPHERAL ASSOCIATIONS
Peripheral to DMA Association
DMAxREQ Register
IRQSEL<6:0> Bits
DMAxPAD Register
Values to Read from
Peripheral
DMAxPAD Register
Values to Write to
Peripheral
INT0 – External Interrupt 0
IC1 – Input Capture 1
OC1 – Output Compare 1 Data
OC1 – Output Compare 1 Secondary Data
IC2 – Input Capture 2
OC2 – Output Compare 2 Data
OC2 – Output Compare 2 Secondary Data
TMR2 – Timer2
TMR3 – Timer3
SPI1 – Transfer Done
UART1RX – UART1 Receiver
UART1TX – UART1 Transmitter
ADC1 – ADC1 convert done
UART2RX – UART2 Receiver
UART2TX – UART2 Transmitter
SPI2 – Transfer Done
ECAN1 – RX Data Ready
PMP – Master Data Transfer
ECAN1 – TX Data Request
DCI – Codec Transfer Done
DAC1 – Right Data Output
DAC2 – Left Data Output
0000000
0000001
0000010
0000010
0000101
0000110
0000110
0000111
0001000
0001010
0001011
0001100
0001101
0011110
0011111
0100001
0100010
0101101
1000110
0111100
1001110
1001111
—
0x0140 (IC1BUF)
—
—
0x0144 (IC2BUF)
—
—
—
—
0x0248 (SPI1BUF)
0x0226 (U1RXREG)
—
0x0300 (ADC1BUF0)
0x0236 (U2RXREG)
—
0x0268 (SPI2BUF)
0x0440 (C1RXD)
0x0608 (PMDIN1)
—
0x0290 (RXBUF0)
—
—
—
—
0x0182 (OC1R)
0x0180 (OC1RS)
—
0x0188 (OC2R)
0x0186 (OC2RS)
—
—
0x0248 (SPI1BUF)
—
0x0224 (U1TXREG)
—
—
0x0234 (U2TXREG)
0x0268 (SPI2BUF)
—
0x0608 (PMDIN1)
0x0442 (C1TXD)
0x0298 (TXBUF0)
0x03F6 (DAC1RDAT)
0x03F8 (DAC1LDAT)
© 2007-2012 Microchip Technology Inc.
DS70292G-page 129