DSPIC33FJ64GP202-ESP Datasheet, PDF (109/436 Pages) Microchip Technology – 16-bit Digital Signal Controllers (up to 128 KB Flash and 16K SRAM) with Advanced Analog

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
DAC1LIE⁽²⁾ DAC1RIE⁽²⁾
—
—
—
—
—
bit 15
U-0
—
bit 8
U-0
—
bit 7
R/W-0
C1TXIE⁽¹⁾
R/W-0
DMA7IE
R/W-0
DMA6IE
R/W-0
CRCIE
R/W-0
U2EIE
R/W-0
U1EIE
U-0
—
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13-7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DAC1LIE: DAC Left Channel Interrupt Enable bit⁽²⁾
1 = Interrupt request enabled
0 = Interrupt request not enabled
DAC1RIE: DAC Right Channel Interrupt Enable bit⁽²⁾
1 = Interrupt request enabled
0 = Interrupt request not enabled
Unimplemented: Read as ‘0’
C1TXIE: ECAN1 Transmit Data Request Interrupt Enable bit⁽¹⁾
1 = Interrupt request occurred
0 = Interrupt request not occurred
DMA7IE: DMA Channel 7 Data Transfer Complete Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
DMA6IE: DMA Channel 6 Data Transfer Complete Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
CRCIE: CRC Generator Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
U2EIE: UART2 Error Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
U1EIE: UART1 Error Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
Unimplemented: Read as ‘0’
Note 1: Interrupts are disabled on devices without ECAN™ modules.
2: Interrupts are disabled on devices without Audio DAC modules.
© 2007-2012 Microchip Technology Inc.
DS70292G-page 109