TC2014 Datasheet, PDF (11/18 Pages) Microchip Technology – 50 mA, 100 mA, 150 mA CMOS LDOs with Shutdown and Reference Bypass

5.0 THERMAL CONSIDERATIONS
5.1 Power Dissipation
The amount of power the regulator dissipates is prima-
rily a function of input voltage, output voltage and
output current.
The following equation is used to calculate worst-case
power dissipation:
EQUATION
PD ≈ (V_INMAX – V_OUTMIN)I_LMAX
Where:
P_D
V_INMAX
V_OUTMIN
I_LMAX
= Worst-case actual power dissipation
= Maximum voltage on V_IN
= Minimum regulator output voltage
= Maximum output (load) current
The maximum allowable power dissipation (P_DMAX) is
a function of the maximum ambient temperature
(T_{AMAX), the maximum allowable die temperature}
(T_JMAX) (+125°C) and the thermal resistance from junc-
tion-to-air (θ_JA). The 5-Pin SOT-23A package has a θ_JA
of approximately 220°C/Watt when mounted on a
typical two layer FR4 dielectric copper clad PC board.
EQUATION
P_DMAX
=
T_{----J--M-----A---X----–-----}T_{---A---M-----A---X-}
θ_JA
Where all terms are previously defined.
TC2014/2015/2185
The P_D equation can be used in conjunction with the
P_DMAX equation to ensure regulator thermal operation
is within limits. For example:
Given:
V_INMAX
V_OUTMIN
I_LOADMAX
T_JMAX
T_AMAX
= 3.0V +10%
= 2.7V – 2.5%
= 40 mA
= +125°C
= +55°C
Find:
1. Actual power dissipation
2. Maximum allowable dissipation
Actual power dissipation:
P_D = (V_INMAX – V_OUTMIN)I_LMAX
= ^[---⁽--³---^.--⁰----^×-----¹---^.--¹---⁾---–-----⁽--²----^.-⁷----^×-----⁰---^.--⁹---⁷---⁵---⁾---^]--⁴---⁰----^×-----¹---⁰---^–---³-
220
= 26.7mW
Maximum allowable power dissipation:
P_DMAX
=
T_{----J--M-----A---X----–-----}T_{---A---M-----A---X-}
θ_JA
= ¹---²---⁵-----–----⁵---⁵--
220
= 318mW
In this example, the TC2014 dissipates a maximum of
only 26.7 mW; far below the allowable limit of 318 mW.
In a similar manner, the P_D equation and P_DMAX equa-
tion can be used to calculate maximum current and/or
input voltage limits.
5.2 Layout Considerations
The primary path of heat conduction out of the package
is via the package leads. Therefore, layouts having a
ground plane, wide traces at the pads and wide power
supply bus lines combine to lower θ_JA and, therefore,
increase the maximum allowable power dissipation
limit.
 2003 Microchip Technology Inc.
DS21662C-page 11