PIC16F87-E Datasheet, PDF (101/228 Pages) Microchip Technology – 18/20/28-Pin Enhan lashMicrocontrollers with nanoWatt Technology

PIC16F87/88
11.1 AUSART Baud Rate Generator
(BRG)
The BRG supports both the Asynchronous and
Synchronous modes of the AUSART. It is a dedicated
8-bit Baud Rate Generator. The SPBRG register
controls the period of a free running 8-bit timer. In Asyn-
chronous mode, bit BRGH (TXSTA<2>) also controls
the baud rate. In Synchronous mode, bit BRGH is
ignored. Table 11-1 shows the formula for computation
of the baud rate for different AUSART modes which
only apply in Master mode (internal clock).
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRG register can be calculated
using the formula in Table 11-1. From this, the error in
baud rate can be determined.
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
baud rate error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.
11.1.1 AUSART AND INTRC OPERATION
The PIC16F87/88 has an 8 MHz INTRC that can be
used as the system clock, thereby eliminating the need
for external components to provide the clock source.
When the INTRC provides the system clock, the
AUSART module will also use the INTRC as its system
clock. Table 11-1 shows some of the INTRC
frequencies that can be used to generate the AUSART
module’s baud rate.
11.1.2 LOW-POWER MODE OPERATION
The system clock is used to generate the desired baud
rate; however, when a low-power mode is entered, the
low-power clock source may be operating at a different
frequency than in full power execution. In Sleep mode,
no clocks are present. This may require the value in
SPBRG to be adjusted.
11.1.3 SAMPLING
The data on the RB2/SDO/RX/DT pin is sampled three
times by a majority detect circuit to determine if a high
or a low level is present at the RX pin.
TABLE 11-1: BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
0
(Asynchronous) Baud Rate = FOSC/(64(X + 1))
1
(Synchronous) Baud Rate = FOSC/(4(X + 1))
Legend: X = value in SPBRG (0 to 255)
BRGH = 1 (High Speed)
Baud Rate = FOSC/(16(X + 1))
N/A
TABLE 11-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Address Name Bit 7 Bit 6 Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
Resets
98h
18h
99h
Legend:
TXSTA CSRC TX9 TXEN SYNC
—
BRGH TRMT TX9D
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
SPBRG Baud Rate Generator Register
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
0000 -010
0000 000x
0000 0000
0000 -010
0000 000x
0000 0000
 2005 Microchip Technology Inc.
DS30487C-page 99