FAN2558 Datasheet, PDF (7/12 Pages) Fairchild Semiconductor – 180mA Low Voltage CMOS LDO

Power Supply Bypassing
The MC100ES8111 is a mixed analog/digital product. The
differential architecture of the MC100ES8111 supports low
noise signal operation at high frequencies. In order to
maintain its superior signal quality, all V_CC pins should be
bypassed by high-frequency ceramic capacitors connected
to GND. If the spectral frequencies of the internally
generated switching noise on the supply pins cross the series
resonant point of an individual bypass capacitor, its overall
impedance begins to look inductive and thus increases with
increasing frequency. The parallel capacitor combination
shown ensures that a low impedance path to ground exists
for frequencies well above the noise bandwidth.
Output Enable/Disable Control
The MC100ES8111 enables and disables outputs
synchronously to the input clock signal. The user may enable
and disable the outputs by using the OE control regardless of
any hold and setup time constraints. Output runt pulses are
prevented in any case. Outputs are disabled in logic low state
(Qn=Low, Qn=High) without a change of the output
impedance.
3.3 V ± 5%
1.8 V ± 0.1 V or
1.5 V ± 0. 1V
33...100 nF
4
33...100 nF
0.1 nF
0.1 nF
V_CC
MC100ES8111
V_CCO
Figure 4. V_CC, V_CCO Power Supply Bypass
CLKn
CLKn
50%
OE
Qn
Qn
t_PDL (OE to Qn)
t_PLE (OE to Qn)
Outputs Disabled
Figure 5. MC100ES8111 Output Disable/Enable Timing
Advanced Clock Drivers Device Data
Freescale Semiconductor
Freescale Confidential Proprietary
NDA Required / Preliminary
MC100ES8111
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